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| copyright ? cirrus logic, inc. 1997 (all rights reserved) CS4235 advanced product databook crystalclear? low cost isa audio system features n compatible with sound blaster?, sound blaster pro?, and windows sound system? n advanced mpc3-compliant input and output mixer n enhanced stereo full duplex operation n dual type-f dma support n integrated crystalclear? 3d stereo enhancement n industry leading delta-sigma data converters (86 db fs a) n internal default pnp resources n cs9236 wavetable interface n cs4610 audio accelerator interface n cs4236b/cs4237b/cs4238b register compatible description the CS4235 is a single chip multimedia audio system that is pin-compatible to the cs423xb for many de- signs. the product includes an integrated fm synthesizer and a plug-and-play interface. in addition, the CS4235 includes hardware master volume control pins as well as extensive power management and 3d sound technology. the CS4235 is compatible with the microsoft ? windows sound system standard and will run software written to the sound blaster and sound blaster pro interfaces. the CS4235 is fully compliant with microsoft's pc'97 and pc'98 audio requirements. ordering info CS4235-jq 100 pin tqfp, 14x14x1.4mm CS4235-kq 100 pin tqfp, 14x14x1.4mm gain gain gain attn l/raux1 l/raux 2 mic min s attn oscillator vref cmaux 2 l/rout input mixer output mixer vref xtali xtalo isa bus interface plug and play codec reg i/f config io irq dma cd-rom or upper address bits decode logic dack table of contents CS4235 performance specifications ... 3 general description ................................. 12 isa bus interface............................................. 13 plug and play ............................................... 15 pnp data ......................................................... 16 loading resource data................................... 16 loading firmware patch data......................... 18 the crystal key ............................................... 18 bypassing plug and play................................. 19 crystal key 2 ................................................... 20 hardware configuration data .......................... 20 hostload procedure ......................................... 24 external e 2 prom............................................ 25 windows sound system codec .............. 26 enhanced functions (modes)........................ 27 fifos ............................................................... 27 wss codec pio register interface ................ 27 dma interface.................................................. 28 sound system codec register interface ........ 29 direct mapped registers (r0-r3) ............... 30 i/o data registers (r3) ............................... 31 indirect mapped registers (i0-i31) .............. 32 wss extended registers (x0-x31) ............ 44 sound blaster interface........................ 53 mode switching ............................................... 53 sound blaster direct register interface.......... 53 sound blaster mixer registers........................ 54 game port interface ................................. 55 control interface ..................................... 57 control register interface................................ 57 control indirect registers (c0-c9) .................. 59 mpu-401 interface ........................................ 62 mpu-401 register interface ............................ 62 midi uart ...................................................... 63 mpu-401 "uart" mode operation ................. 63 fm synthesizer ............................................. 63 cdrom interface ......................................... 64 cs4610 dsp serial data port .................. 64 cs9236 wavetable serial data port ... 66 wss codec software description .......67 calibration ........................................................67 changing sampling rate .................................68 changing audio data formats.........................69 audio data formats .........................................69 dma registers .................................................69 wss codec interrupt .......................................71 error conditions ...............................................71 digital hardware description...............72 bus interface ....................................................72 volume control interface .................................72 crystal/clock ....................................................73 general purpose output pins ..........................73 reset and power down ...................................73 address port configuration ..............................73 multiplexed pin configuration ..........................74 analog hardware description .............74 line-level inputs plus mpc mixer...................74 microphone level input ....................................75 mono input .......................................................75 line-level outputs ...........................................75 miscellaneous analog signals .........................76 grounding and layout ..............................76 power supplies.............................................76 adc/dac filter response..........................78 pin descriptions ...........................................80 isa bus interface pins .....................................81 analog inputs ...................................................82 analog outputs.................................................83 midi interface...................................................84 external peripheral signals..............................84 joystick interface..............................................85 cs4610 dsp serial port interface...................85 cs9236 wavetable serial port interface .........85 cdrom interface.............................................86 volume control.................................................87 miscellaneous...................................................87 power supplies ................................................88 parameter definitions...............................89 package parameters .................................90 appendix a: default pnp data.................91 appendix b: CS4235 differences .............93 crd4235-8 crystalclear 16-bit audio motherboard example design tm ds252pp2 windows 95 and windows 3.1 are trademarks; microsoft, windows and windows sound system are registered trademarks of microsoft corporation. sound blaster and sound blaster pro are trademarks of creative labs. ad lib is a trademark of adlib corporation. crystalclear is a trademark of cirrus logic, inc. 2 analog characteristics (t a = 25 c; va, vd1, vdf1-vdf3 = +5 v; input levels: logic 0 = 0 v, logic 1 = vd1; 1 khz input sine wave; sample frequency, fs = 44.1 khz; measurement bandwidth is 20 hz to 20 khz, 16-bit linear coding.) CS4235-jq CS4235-kq parameter* symbol min typ max min typ max units analog input characteristics (a-d-pc) - volume set to 0 db unless otherwise specified. adc1 resolution (note 1) 16 - - 16 - - bits adc1 differential nonlinearity (note 1) - - 0.5 -- 0.5 lsb frequency response: ac = 1 db fr - - - 20 19000 hz dynamic range aux1, aux2 (note 2) mic dr - - -80 -75 - - -80 -72 -85 -80 - - db fs a db fs a total harmonic distortion+noise aux1, aux2 -3 db fs input (note 2) mic thd+n - - -66 -66 - - -75 -72 -80 -80 - - db fs a db fs a interchannel isolation (note 1): left to right 10 khz input aux1/2 to mic aux1 to aux2 - - - -80 -80 -80 - - - -70 - - -80 -80 -90 - - - db db db interchannel gain mismatch aux1, aux2 mic - - - - 0.5 0.5 - - - - 0.5 0.5 db db adc1 offset error 0 db gain - - - - 10 200 lsb full scale input voltage: (mge/mbst=1) mic (mge/mbst=0) mic aux1, aux2, min 0.25 2.5 2.5 0.28 2.8 2.8 - - - 0.25 2.5 2.5 0.28 2.8 2.8 - - - v pp v pp v pp gain drift - 100 -- 100 -ppm/c input resistance (note 1): mic aux1, aux2, min 8 20 11 23 - - 8 20 11 23 - - k w k w input capacitance (note 1) - - 15 - - 15 pf notes: 1. this specification is guaranteed by characterization, no production testing. 2. mge or mbst = 1 (see wss indirect reg i0 or x2). *parameter definitions are given at the end of this data sheet. specifications are subject to change without notice. crystalclear low cost isa audio system tm CS4235 ds252pp2 3 analog characteristics (continued) CS4235-jq CS4235-kq parameter* symbol min typ max min typ max units analog output characteristics (pc-d-a) - volume set to 0 db unless otherwise specified. dac1 resolution (note 1) 16 - - 16 - - bits dac1 differential nonlinearity (note 1) - - 0.5 -- 0.5 lsb dac1 frequency response: ac = 1 db fr - - - 20 - 19000 hz dac1 dynamic range dr - -86 - -80 -86 - db fs a dac1 total harmonic distortion+noise: -3 db fs input (note 3) thd+n - -80 - -74 -80 - db fs a dac1 interchannel isolation (notes 1,3) - -95 - -80 -95 - db dac1 interchannel gain mismatch - 0.1 0.5 - 0.1 0.5 db voltage reference output - vref 2.0 2.2 2.5 2.0 2.2 2.5 v voltage reference output current - vref (notes 1,4) - 100 400 - 100 400 m a dac1 programmable attenuation span 90 94.5 - 90 94.5 - db dac1 atten. step size: greater than -82.5 db -82.5 db to -94.5 db 1.3 1.0 1.5 1.5 1.7 2 1.3 1.0 1.5 1.5 1.7 2 db db dac1 offset voltage - - - - 1 10 mv full scale output voltage (note 3) 2.5 2.8 3.3 2.5 2.8 3.3 vpp gain drift (note 1) - 100 - - 100 - ppm/c deviation from linear phase (note 1) (passband) - - 1 - - 1 degree external load impedance (note 1) 10 - - 10 - - k w mute attenuation (note 1) 80 - - 80 - - db power supply power supply current digital, operating analog, operating total operating total power down - - - - 70 30 100 - - - - - - - - - 70 30 100 - 80 35 - 1 ma ma ma ma power supply rejection, 1 khz (note 1) 40 - - 40 - - db notes: 3. 10 k w , 100 pf load. 4. dc current only. if dynamic loading exists, then the voltage reference output must be buffered or the performance of adcs and dacs will be degraded. crystalclear low cost isa audio system tm CS4235 4 ds252pp2 absolute maximum ratings (agnd, dgnd, sgnd = 0 v, all voltages with respect to 0 v.) parameter symbol min max units power supplies: digital analog vd1 vdf1-vdf3 va -0.3 -0.3 -0.3 6.0 6.0 6.0 v v v total power dissipation (supplies, inputs, outputs) - 1 w input current per pin (except supply pins) -10.0 +10.0 ma output current per pin (except supply pins) -50 +50 ma analog input voltage -0.3 va+0.3 v digital input voltage: sa<15:0>, ior, iow, aen sd<7:0>, dack digital characteristics (t a = 25 c; va, vdf1-vdf3 = +5 v, vd1 = +5 v; agnd, dgnd1, sgnd1-sgnd4 = 0 v.) parameter symbol min max units high-level input voltage up/down/mute other digital inputs xtali v ih 3.0 2.0 vdf-1.0 - - - v v v low-level input voltage v il -0.8v high-level output voltage: isa bus pins i 0 = -24.0 ma iochrdy, sda (note 6) all others i 0 = -1.0 ma v oh 2.4 - 2.4 vd1 vdf vdf v v v low-level output voltage: isa bus pins i 0 = 24.0 ma mclk, sdout, midout, iochrdy i 0 = 8.0 ma all others i 0 = 4.0 ma v ol - - - 0.4 0.4 0.4 v v v input leakage current (digital inputs) -10 10 m a output leakage current (high-z digital outputs) -10 10 m a note 6. open collector pins. high level output voltage dependent on external pull up (required) used and number of peripherals (gates) attached. adc1/dac1 digital filter characteristics (note 1) parameter symbol min typ max units passband 0 - 0.40xfs hz frequency response -1.0 - +0.5 db passband ripple (0-0.40xfs) - - 0.1 db transition band 0.40xfs - 0.60xfs hz stop band 0.60xfs - - hz stop band rejection 74 - - db group delay - - 10/fs s group delay variation vs. frequency adc1 dac1 - - - - 0.0 0.1/fs m s m s recommended operating conditions (agnd, dgnd, sgnd = 0 v, all voltages with respect to 0 v.) parameter symbol min typ max units power supplies: digital (note 5) digital filtered analog vd1 vdf1-vdf3 va 4.75 4.75 4.75 5.0 5.0 5.0 5.25 5.25 5.25 v v v operating ambient temperature t a 02570c note 5: vd1 supplies the power to the isa interface pins. crystalclear low cost isa audio system tm CS4235 6 ds252pp2 timing parameters (t a = 25 c; va, vd1, vdf1-vdf3 = +5 v; outputs loaded with 30 pf; input levels: logic 0 = 0 v, logic 1 = vdf, rise/fall time = 2 ns; input/output reference levels = 2.5 v) parameter symbol min max units e 2 prom timing (note 1) scl low to sda data out valid t aa 03.5 m s start condition hold time t hd:sta 4.0 - m s clock low period t lscl 4.7 - m s clock high period t hscl 4.0 - m s start condition setup time (for a repeated start condition) t su:sta 4.7 - m s data in hold time t hd:dat 0- m s data in setup time t su:dat 250 - ns sda and scl rise time (note 7) t r -1 m s sda and scl fall time t f - 300 ns stop condition setup time t su:sto 4.7 - m s data out hold time t dh 0-ns notes 7. rise time on sda is determined by the capacitance of the sda line with all connected gates and the external pullup resistor required. scl sda (in) sda (out) t f t hscl t lscl t r t su:sta t hd:sta t hd:dat t su:dat t su:sto t aa t dh e 2 prom 2-wire interface timing crystalclear low cost isa audio system tm CS4235 ds252pp2 7 timing parameters (continued) parameter symbol min max units parallel bus timing iow or ior strobe width t stw 90 - ns data valid to iow rising edge (write cycle) t wdsu 22 - ns ior falling edge to data valid (read cycle) t rddv -60ns sa <> and aen setup to ior or iow falling edge t adsu 22 - ns sa <> and aen hold from iow or ior rising edge t adhd 10 - ns dack<> inactive to iow or ior falling edge (dma cycle immediately followed by a non-dma cycle) (note 8) t sudk1 60 - ns dack<> active from iow or ior rising edge (non-dma cycle completion followed by dma cycle) (note 8) t sudk2 0-ns dack<> setup to ior falling edge (dma cycles) dack<> setup to iow falling edge (note 8) t dksua t dksub 25 25 - - ns ns data hold from iow rising edge t dhd2 15 - ns drq<> hold from iow or ior falling edge dtm(i10) = 0 (assumes no more dma cycles needed) dtm(i10) = 1 t drhd - -25 45 - ns time between rising edge of iow or ior to next falling edge of iow or ior t bwdn 80 - ns data hold from ior rising edge t dhd1 025ns dack<> hold from iow rising edge dack<> hold from ior rising edge t dkhda t dkhdb 25 25 - - ns ns resdrv pulse width high (note 1) t resdrv 1-ms initialization time (note 1, 9) t init 310ms eeprom read time (note 1, 10) t eeprom 1190ms xtal, 16.9344 mhz, frequency (notes 1, 11) 16.92 16.95 mhz xtali high time (notes 1, 11) 24 - ns xtali low time (notes 1, 11) 24 - ns sample frequency (note 1) fs 3.918 50 khz cs4610 dsp serial port timing sclk rising to sdout valid (note 1) t pd1 -60ns sclk rising to fsync transition (note 1) t pd2 -20 20 ns sdin valid to sclk falling (note 1) t s1 30 - ns sdin hold after sclk falling (note 1) t h1 30 - ns notes: 8. aen must be high during dma cycles. 9. initialization time depends on the power supply circuitry, as well as the the type of clock used. 10. eeprom read time is dependent on amount of data in eeprom. minimum time relates to no eeprom present. maximum time relates to eeprom data size of 1k bytes. 11. the sample frequency specification must not be exceeded. crystalclear low cost isa audio system tm CS4235 8 ds252pp2 t drhd t dkhdb t dhd1 t rddv t dksua t stw drq<> dack<> sd<7:0> ior 8-bit mono dma read/capture cycle sdin sdout t pd1 t s1 t h1 msb, left sclk t pd2 t pd2 fsync t sckw msb, left t pd2 fsync sf1,0=01,10 sf1,0=00 cs4610 dsp serial port timing scl/sda eeprom read t resdrv resdrv sd<> sa<> codec responds to isa activity t init t eeprom reset timing crystalclear low cost isa audio system tm CS4235 ds252pp2 9 right/low byte left/low byte t bwdn sd<7:0> drq<> left/high byte right/high byte ior/iow dack<> 16-bit stereo dma cycle left/low byte t bwdn sd<7:0> drq<> right/high byte dack<> ior/iow 8-bit stereo or 16-bit mono dma cycle t drhd t stw drq<> dack<> sd<7:0> iow t dksub t dkhda t dhd2 t wdsu 8-bit mono dma write/playback cycle crystalclear low cost isa audio system tm CS4235 10 ds252pp2 drq<> sd<> sa<> t adsu t adhd t sudk1 t sudk2 t dhd2 t wdsu t stw iow dack<> aen i/o write cycle drq<> sd<> sa<> t dhd1 t rddv t adsu t adhd t sudk1 t sudk2 ior dack<> aen i/o read cycle crystalclear low cost isa audio system tm CS4235 ds252pp2 11 general description this device is comprised of six physical devices along with plug-and-play support for one addi- tional external device. the internal devices are: windows sound system codec sound blaster pro compatible interface game port (joystick) control mpu-401 fm synthesizer the external device is: ide cdrom on power up, this part requires a resdrv sig- nal to initialize the internal configuration. when initially powered up, the part is isolated from the bus, and each device supported by the part must be activated via software. once activated, each device responds to the resources given (address, irq, and dma channels). the devices listed above are grouped into five logical devices, as shown in figure 1 (bracketed features are sup- ported, but typically not used). the five logical devices are: logical device 0: windows sound system codec (wss codec) adlib/sound blaster-compatible synthesizer sound blaster pro compatible interface logical device 1: game port logical device 2: control logical device 3: mpu401 logical device 4: cdrom logical device 0 consists of three physical de- vices. the wss codec and the synthesizer are grouped together since the original windows sound system card expected an fm synthesizer if the codec was present. the sound blaster pro compatible interface, sbpro, is also grouped to allow the wss codec and the sbpro to share interrupts and dma channels. the wss codec, fm synthesizer, and the sbpro compatible de- vices are internal to the part. logical device 1 is the game port that supports up to two joystick devices. logical device 2 is the control device that sup- ports global features of the part. this device uses i/o locations to control power management, joystick rate, and pnp resource data loading. logical device 3 is the mpu-401 interface. the mpu-401 midi interface includes a 16-byte fifo for data transmitted out the midout pin and a 16-byte fifo for data received from the midin pin. logical device 4 supports an ide cdrom de- vice. although this logical device is listed as a cdrom, any external device that fits within the resources listed above may be substituted. this interface, is generic and can support devices us- ing 1 to 127 i/o locations for the base address, 1 to 8 i/o locations for the alternate base address, an interrupt, and a dma channel. isa bus interface the 8-bit parallel i/o and 8-bit parallel dma ports provide an interface which is compatible with the industry standard architecture (isa) bus. the isa interface enables the host to com- municate with the various functional blocks within the part via two types of accesses: pro- grammed i/o (pio) access, and dma access. a number of configuration registers must be pro- grammed prior to any accesses by the host computer. the configuration registers are pro- grammed via a plug-and-play configuration sequence or via configuration software provided by cirrus logic. ds252pp2 CS4235 crystalclear low cost isa audio system tm 12 i/o cycles every device that is enabled, requires i/o space. an i/o cycle begins when the part decodes a valid address on the bus while the dma ac- knowledge signals are inactive and aen is low. the ior and iow signals determine the direc- tion of the data transfer. for read cycles, the part will drive data on the sd<7:0> lines while the host asserts the ior strobe. write cycles require the host to assert data on the sd<7:0> lines and strobe the iow signal. data is latched on the ris- ing edge of the iow strobe. i/o address decoding the logical devices use 10-bit or 12-bit address decoding. the synthesizer, sound blaster, game port, mpu-401, and cdrom devices support 10-bit address decoding, while the windows sound system and control devices support 12- bit address decoding. devices that support 10-bit address decoding, require a10 and a11 be zero for proper decode; therefore, no aliasing occurs through the 12-bit address space. to prevent aliasing into the upper address space, a "16-bit decode" option may be used, where the upper address bits sa12 through sa15 are con- nected to the part. sa12-sa15 are then decoded to be 0,0,0,0 for all logical device address de- coding. when the upper address bits are used, the cdrom interface is no longer available since the upper address pins are multiplexed with the cdrom pins (see reset and power down section). if the cdrom is needed, the circuit shown in figure 2 can replace the sa12 through sa15 pins and provide the same func- tionality. four cascaded or gates, using a 74als32, can replace the als138 in figure 2, but causes a greater delay in address decoding. pnp isa bus interface wss codec: i/o: wssbase 2 dma chan. 1 interrupt logical device 0 game port: i/o: gamebase logical device 1 control: i/o: ctrlbase [1 interrupt] logical device 2 mpu-401: i/o: mpubase 1 interrupt logical device 3 cdrom: i/o: cdbase acdbase [1 interrupt] [1 dma chan.] logical device 4 synthesis: i/o: synbase [1 interrupt] sbpro: i/o: sbbase (dma shared) (interrupt shared) figure 1. logical devices ds252pp2 CS4235 crystalclear low cost isa audio system tm 13 dma cycles the part supports up to three 8-bit isa-compat- ible dma channels. the default hardware connections, which can be changed through the hardware configuration data, are: dma a = isa dma channel 0 dma b = isa dma channel 1 dma c = isa dma channel 3 the typical configuration would require two dma channels. one for the wss codec and sound blaster playback, and the other for wss codec capture (to support full-duplex). the cdrom, if used, can also support a dma chan- nel, although this is not typical. dma cycles are distinguished from control reg- ister cycles by the generation of a drq (dma request). the host acknowledges the request by generating a dack (dma acknowledge) sig- nal. the transfer of audio data occurs during the dack cycle. during the dack cycle the ad- dress lines are ignored. the digital audio data interface uses dma re- quest/grant pins to transfer the digital audio data between the part and the isa bus. upon receipt of a dma request, the host processor responds with an acknowledge signal and a command strobe which transfers data to and from the part, eight bits at a time. the request pin stays active until the appropriate number of 8-bit cycles have occurred. the number of 8-bit transfers will vary depending on the digital audio data format, bit resolution, and operation mode. the dma request signal can be asserted at any time. once asserted, the dma request will re- main asserted until a complete dma cycle occurs. a complete dma cycle consists of one or more bytes depending on which device inter- nal to the part is generating the request. interrupts for plug-and-play flexibility, seven interrupt pins are supported, although only one or two are typically used. the default hardware connec- tions, which can be modified through the hardware configuration data, are: irq a = isa interrupt 5 irq b = isa interrupt 7 irq c = isa interrupt 9 irq d = isa interrupt 11 irq e = isa interrupt 12 irq f = isa interrupt 15 irq g is new and defaults to not being con- nected for backwards compatibility. this new interrupt pin would typically be connected to isa interrupt 10. new designs that use irq g must change the hardware configuration data to indicate which isa interrupt is connected to irq g. the typical configuration would support two in- terrupt sources: one shared between the wss codec and the sound blaster pro compatible de- vices, and the other for the mpu401 device. interrupts are also supported for the fm synthe- sizer, control, and cdrom devices, but are typically not used. sa12 sa13 sa14 sa15 aen +5v 1 4 c b a 3 2 15 g1 6 g2b g2a 5 y0 y6 y5 y4 y3 y2 y1 y7 74als138 aen isa bus figure 2. 16-bit decode circuit ds252pp2 CS4235 crystalclear low cost isa audio system tm 14 plug and play the plug-and-play (pnp) interface logic is com- patible with the intel/microsoft plug-and-play specification, version 1.0a, for an isa-bus de- vice. since the part is an isa-bus device, it only supports isa-compatible irqs and dma chan- nels. plug and play compatibility allows the pc to automatically configure the part into the sys- tem upon power up. plug and play capability optimally resolves conflicts between plug and play and non-plug and play devices within the system. alternatively, the pnp feature can be by- passed. see the bypassing pnp section for more information. for a detailed plug-and-play proto- col description, please refer to the plug and play isa specification . to support plug-and-play in isa systems that do not have a pnp bios or a pnp-aware operating system, the configuration manager (cm) tsr and an isa configuration utility (icu) from in- tel corp. are used to provide these functions. the cm isolates the cards, assigns card select numbers, reads pnp card resource requirements, and allocates resources to the cards based on system resource availability. the icu is used to keep the bios and the cm informed of the cur- rent system configuration. it also aids users in determining configurations for non-pnp isa cards. a more thorough discussion of the con- figuration manager and the isa configuration utility can be found in the product development information document of the plug and play kit by intel corp. in a pnp bios system, the bios is responsible for configuring all system board pnp devices. some systems require additional software to aid the bios in configuring pnp isa cards. the pnp bios can execute all pnp func- tions independently of the type of operating system. however, if a pnp aware operating sys- tem is present, the pnp responsibilities are shared between the bios and the operating system. for more information regarding pnp bios, please refer to the latest revision of the plug and play bios specification published by compaq com- puter, phoenix technologies, and intel. the plug and play configuration sequence maps the various functional blocks of the part (logical devices) into the host system address space and configures both the dma and interrupt channels. the host has access to the part via three 8-bit auto-configuration ports: address port (0279h), write data port (0a79h), and relocatable read data port (020bh - 03ffh). the read data port is relocated automatically by pnp software when a conflict occurs. note that the address port can be moved for motherboard devices. see the ad- dress port configuration section for more details. the configuration sequence is as follows: 1. host sends a software key which places all pnp cards in the sleep state (or plug-and- play mode). 2. the CS4235 is isolated from the system using an isolation sequence. 3. a unique identifier (handle) is assigned to the part and the resource data is read. 4. after all cards resource requirements are de- termined, the host uses the handle to assign conflict-free resources 5. after the configuration registers have been programmed, each configured logical device is activated. 6. the part is then removed from plug-and-play mode. upon power-up, the chip is inactive and must be enabled via software. the CS4235 monitors writes to the address port . if the host sends a pnp initiation key, consisting of a series of 32 predefined byte writes, the hardware will detect ds252pp2 CS4235 crystalclear low cost isa audio system tm 15 the key and place the part into the plug-and-play (pnp) mode. another method to program the part is to use a special crystal initiation key which functions like the pnp initiation key, but can be invoked by the user at any time. however, the crystal key only supports one audio codec per system. the crystal key and special commands are detailed in the crystal key and bypassing pnp sections. the isolation sequence uses a unique 72-bit se- rial identifier. the host performs 72 pairs of i/o read accesses to the read data port. the identi- fier determines what data is put on the data bus in response to those read accesses. when the iso- lation sequence is complete, the cm assigns a card select number (csn) to the part. this number distinguishes the CS4235 from the other pnp devices in the system. the configuration manager (cm) then reads the resource data from the CS4235. the 72-bit identifier and the re- source data is either stored in an external user-programmable e 2 prom, or loaded via a "hostload" procedure from bios before pnp software is initiated. the cm determines the necessary resource re- quirements for the system and then programs the part through the configuration registers. the con- figuration register data is written one logical device at a time. after all logical devices have been configured, cm activates each device indi- vidually. each logical device is now available on the isa bus and responds to the programmed address range, dma channels, and interrupts that have been allocated to that logical device. pnp data hardware configuration and plug-and-play re- source data can be loaded into the parts ram. the data may be stored in an external e 2 prom or may be downloaded from the host. internal default pnp data is provided for motherboard de- signs. to load the data, refer to the loading resource data section. the following is the plug-and-play resource data: the first nine bytes of the pnp resource data are the plug-and-play id, which uniquely identifies the audio codec from other pnp devices. the pnp id is broken down as follows: 0eh, 63h - crystal id - csc in compressed ascii. (see the pnp spec for more information) 42h - oem id. a unique oem id must be ob- tained from crystal for each unique crystal product used. 25h - crystal product id for the CS4235 ffh, ffh, ffh, ffh - serial number. this can be modified by each oem to uniquely identify their card. ??h - checksum. of the 9-byte serial number listed above, cirrus software uses the first two bytes to indicate the presence of a CS4235, and the fourth byte, 0x25, to indicate the CS4235; therefore, these three bytes must not be altered. the default pnp id, in hex, is 0e634236ffffffffa9 for backwards compatibility. the next 3 bytes are the pnp version number. the default is version 1.0a: 0ah, 10h, 05h. the next sequence of bytes are the ansi identi- fier string. the default is: 82h, 0eh, 00h, crystal codec, 00h. the logical device data must be entered using the pnp isa specification format. typical logical device values are found in table 1. internal de- fault e 2 prom data is found in appendix a. loading resource data a serial e 2 prom interface allows user-program- mable serial number and resource data to be stored in an external e 2 prom. the interface is compatible with devices from a number of ven- ds252pp2 CS4235 crystalclear low cost isa audio system tm 16 dors and the size may vary according to specific customer requirements. the maximum size for resource data supported by the parts internal ram is 384 bytes of combined hardware con- figuration and pnp resource data. with the addition of the 4-byte header, the maximum amount of e 2 prom space used would be 388 bytes. however, the part also supports firmware upgrades via the e 2 prom. to support firmware upgrades, the e 2 prom size must be greater than 770 bytes. after power-up, the existence of an e 2 prom is checked by reading the first two bytes from the e 2 prom interface. if the first two bytes from the e 2 prom port read 55h and bbh, then the rest of the e 2 prom data is loaded into the internal ram. if the first two bytes arent correct, the e 2 prom is assumed not to exist. for motherboard designs, internal de- fault pnp data is provided or a hostload sequence can be used to update the resource data. if the part is installed on a plug-in card, then an external e 2 prom is required to ensure that the proper pnp resource data is loaded into the internal ram prior to a pnp sequence. see physical device logical device best choice acceptable choice 1 sub optimal choice 1 sub optimal choice 2 wss 0 ansi id = csc0000 ansi id = wss/sb 16-bit address decode wssbase length/alignment 534h 4/4 534-ffch 4/4 534-ffch 4/4 high true edge sensitive irq 5 (sb share) 5,7,9,11,12,15 (sb share) 5, 7, 9, 11, 12, 15 (sb share) 8-bit, count by byte, type a dma0 (playback) 1 (sb share) 1, 3 (sb share) 0, 1, 3 (sb share) same dma1 (record) 0, 3 0, 1, 3 ---- synthesis 0 16-bit address decode synbase length/alignment 388h 4/8 388h 4/8 388-3f8h 4/8 irq ---- ---- ---- sb pro 0 16-bit address decode sbbase length/alignment 220h 16/32 220-260h 16/32 220-300h 16/32 game port 1 ansi id = csc0001 ansi id = game 16-bit address decode gamebase length/alignment 200h 8/8 208h 8/8 control 2 ansi id = csc0010 ansi id = ctrl 16-bit address decode ctrlbase length/alignment 120-ff8h 8/8 irq ---- mpu401 3 ansi id = csc0003 ansi id = mpu 16-bit address decode mpubase length/alignment 330h 2/8 330-360h 2/8 330-3e0h 2/8 irq 9 9,11,12,15 ---- ---- feature not supported in the listed configuration, but is supported through customization. table 1. typical motherboard plug-and-play resource data ds252pp2 CS4235 crystalclear low cost isa audio system tm 17 the external e 2 prom section for more informa- tion on the serial e 2 prom interface and e 2 prom programming. the format for the data stored in the e 2 prom is as follows: 2 bytes e 2 prom validation: 55h, bbh 2 bytes length of resource data in e 2 prom 19 bytes hardware configuration 9 bytes plug and play id 3 bytes plug and play version number variable number of bytes of user defined ascii id string logical device 0 (windows sound system, fm synthesizer, sound blaster pro) data logical device 1 ( game port) data logical device 2 ( control) data logical device 3 ( mpu-401) data logical device 4 ( cd-rom) data end of resource byte & checksum byte firmware patch code. the default internal e 2 prom data, in assembly format, can be found in appendix a. loading firmware patch data an external e 2 prom is read during the power- up sequence that stores hardware configuration and pnp data, and firmware patch data. the part contains ram and rom to run the core proces- sor. the ram allows updates to the core processor functionality. placing the firmware patches in e 2 prom, gives the maximum func- tionality at power-up without the need for a software driver. the firmware patch data is typically included at the end of the pnp resource data. cirrus provides a utility that will read in patch data from a file, and append it to the pnp resource data. the patch file must be obtained from cirrus. the crystal key note: the crystal key cannot differentiate be- tween multiple cirrus audio codecs in a system; therefore, only one audio part is allowed in systems using the crystal key. to allow multiple parts in a system, the plug-and-play isolation se- quence must be used since it supports multiple parts via the serial identifier used in the isolation sequence. crystal key 2 is also designed to al- low motherboard and add-in card chips to co-exist in a system. the crystal key places the part in the configura- tion mode. once the crystal key has been initiated, an alternate method of programming the configuration registers may be used. this al- ternate method is referred to as the "slam" method. the slam method allows the user to directly access the configuration registers, con- figure, and activate the chip, and then, optionally, disable the pnp and/or crystal key feature. the slam method uses commands that are similar to the pnp commands; however, they are different since the user has direct access to the configuration registers. to use the slam method, see the bypassing pnp section. the following 32 bytes, in hex, are the crystal key: 96, 35, 9a, cd, e6, f3, 79, bc, 5e, af, 57, 2b, 15, 8a, c5, e2, f1, f8, 7c, 3e, 9f, 4f, 27, 13, 09, 84, 42, a1, d0, 68, 34, 1a ds252pp2 CS4235 crystalclear low cost isa audio system tm 18 bypassing plug and play the slam method allows the user to bypass the plug and play features and, as an option, allows the part to act like a non-plug and play or legacy device; however, the slam method only sup- ports one cirrus audio ic per system. the user directly programs the resources into the part, and then optionally disables the pnp and/or the crys- tal key, which forces the part to disregard any future pnp or crystal initiation key sequences (all activated logical devices appear as legacy devices to pnp). the crystal and pnp keys can also be disabled through the e 2 prom. the slam method uses the address port (ap) simi- larly to plug-and-play. although the standard ap is 279h, two other selections are available for non-standard implementations. see the address port configuration section for more details. to use the slam method, the following se- quence must be followed: 1. host sends 32-byte crystal key to the ap, chip enters configuration mode. 2. host programs csn (card select number) by writing a 06h and 00h to the ap. 3. host programs the configuration registers of each logical device by writing to the ap. the following data is the maximum amount of in- formation per device. all current devices only need a subset of this data: logical device id (15h, xxh) xxh is logical device number: 0-5 i/o port base address 0 (47h, xxh, xxh) high byte , low byte i/o port base address 1 (48h, xxh, xxh) high byte , low byte i/o port base address 2 (42h, xxh, xxh) high byte , low byte interrupt select 0 (22h, xxh) interrupt select 1 (27h, xxh) dma select 0 (2ah, xxh) dma select 1 (25h, xxh) activate device (33h, 01h) (33h, 00h deactivates a device) 4. repeat #3 for each logical device to be en- abled. (not all devices need be enabled.) 5. host activates chip by writing a 79h to ap. 6. (optional) host disables pnp key by writing a 55h to ctrlbase+5. the part will not par- ticipate in any future pnp cycles. the crystal key can also be disabled by writing a 56h to ctrlbase+5. note: to enable the pnp/crystal keys after they have been disabled by the slam method, bring the resdrv pin to a logic high or remove power from the device. the following illustrates typical data sent using the slam method. 006h, 001h ; csn=1 015h, 000h ; logical device 0 047h, 005h, 034h ; wssbase = 0x534 048h, 003h, 088h ; synbase = 0x388 042h, 002h, 020h ; sbbase = 0x220 022h, 005h ; wss & sb irq = 5 02ah, 001h ; wss & sb dma0 = 1 025h, 003h ; wss capture dma1 = 3 033h, 001h ; activate logical device 0 015h, 001h ; logical device 1 047h, 002h, 000h ; gamebase = 0x200 033h, 001h ; activate logical device 1 ds252pp2 CS4235 crystalclear low cost isa audio system tm 19 015h, 002h ; logical device 2 047h, 001h, 020h ; ctrlbase = 0x120 033h, 001h ; activate logical device 2 015h, 003h ; logical device 3 047h, 003h, 030h ; mpubase=0x330 022h, 009h ; mpu irq = 9 033h, 001h ; activate logical device 3 079h ; activate audio device if all the above data is sent, after the crystal key, all devices except the cdrom will respond to the appropriate resources given. crystal key 2 a new feature of this part is the addition of an- other way to bypass the pnp interface using a new key, designated crystal key 2 (ck2). this new key is designed for codecs on the mother- board that are hidden from normal pnp. the following 32 bytes, in hex, are crystal key 2 followed by the upper 8 bits of the read data port (rdp): 95, b1, d8, 6c, 36, 9b, 4d, a6, d3, 69, b4, 5a, ad, d6, eb, 75, ba, dd, ee, f7, 7b, 3d, 9e, cf, 67, 33, 19, 8c, 46, a3, 51, a8, (hostload), the first four bytes are not needed; therefore, the configuration data is only 19 bytes long. the configuration data maps the many functions of the logical devices to the physical pins of the chip. table 2 lists the hardware con- figuration bytes. the detailed bit descriptions for each byte follows. while the reserved bits are listed as "res" in the bit position (and should be written to 0), "rbc" is "reserved, backwards com- patible" for bits that were used on previous chips, but are no longer required on this chip. these bits are read/writable but should generally be set to 0 for backwards compatibility. byte default description 155h e 2 prom validation byte 1. the first two bytes indicate that the e 2 prom exists. 2 bbh e 2 prom validation byte 2 3 00h high byte for length of data in e 2 prom 4 ddh low byte for length of data in e 2 prom 5 00h alternate cdrom (logical device 4), acdbase, address length mask 6 03h reserved 7 80h misc. configuration bits: cdrom interrupt polarity, key disables, vcen 8 00h global configuration byte: ifm, vcf1, wten 9 05h code base byte 10 20h fm volume scaling 11* 04h reserved - must be 0x04 12* 08h reserved - must be 0x08 13* 10h reserved - must be 0x10 14 80h mono and dsp port control 15 00h e 2 prom checksum 16 00h global configuration byte 2: eecs, aux1r, 3den, dspd1, psh 17 08h cdrom (logical device 4), cdbase, address length 18* 48h reserved - must be 0x48 19 75h irq a/b selection: lower nibble = a, upper nibble = b. along with next two bytes - specify hardware interrupts tied to irqa-irqf pins 20 b9h irq c/d selection: lower nibble = c, upper nibble = d. 21 fch irq e/f selection: lower nibble = e, upper nibble = f. 22 10h dma a/b selection: lower nibble = a, upper nibble = b. this byte and the next byte specify hardware drq/dacks tied to the dmaa-dmac pins and the 7th irq pin - irq g 23 03h dma c/irq g selection: lower nibble = dma c, upper nibble = irq g note:the first four bytes are exclusive to the e 2 prom and are not used in the hostload mode. * currently not supported. must be set to default values given in the table. table 2. hardware configuration data ds252pp2 CS4235 crystalclear low cost isa audio system tm 21 hw config. byte 5: acdbase address length mask, default = 00000000 d7 d6 d5 d4 d3 d2 d1 d0 res res res res res cm2 cm1 cm0 cm2-cm0 address bit masks for the alternate cdrom address decode, acdbase. see the cdrom interface section for more details on acdbase. acdbase must be on the same para- graph boundry as the address lengh decode. 000 - acdcs low for 1 byte 001 - acdcs low for 2 bytes 011 - acdcs low for 4 bytes 111 - acdcs low for 8 bytes xxx - all others, reserved hw config. byte 7: misc. configuration bits, default = 10000000 d7 d6 d5 d4 d3 d2 d1 d0 ihcd rbc pkd ckd ck2d vcen rbc rbc vcen volume control enable. when set, the up, down, and mute pins be- come active and provide a hardware master volume control. ck2d crystal key 2 disable. when set, blocks the part from receiving the 2nd crystal key. ckd crystal key disable. when set, blocks the part from receiving the crystal key. pkd pnp key disable. when set, blocks the part from receiving the plug-and- play key. ihcd interrupt high - cdrom. when set, cdint is active high. when clear, cdint is active low. hw config. byte 8: global configuration byte, default = 10000000 d7 d6 d5 d4 d3 d2 d1 d0 ifm vcf1 rbc res wten rbc res res wten wavetable serial port enable. when set, enables the cs9236 single- chip wavetable music synthesizer serial port pins. this function is also available in c8. note: the dsp spe bit in i16 must be 0 for the wavetable port to be enabled. vcf1 hardware volume control format. this bit controls the format of the hardware volume control pins up, down, and mute. the volume con- trol is enabled by setting vcen in the previous hardware configuration byte. vcf1 is also available through c8. 0 - mute is a momentary switch. mute toggles between mute and un-mute. pressing the up or down switch always un-mutes. 1 - mute is not used. two button volume control. pressing the up and down buttons simultaneously causes the volume to mute. pressing up or down un-mutes. ifm internal fm. when set, the internal fm synthesizer is enabled. when clear, fm is disabled. hw config. byte 9: code base byte, default = 00000101 d7 d6 d5 d4 d3 d2 d1 d0 cb7 cb6 cb5 cb4 cb3 cb2 cb1 cb0 cb7-cb0 code base byte. determines the code base located in the e 2 prom. if not correct, the firmware code after the pnp resource data is not loaded. 0x05 - CS4235 e 2 prom load 0x06 - CS4235 host load ds252pp2 CS4235 crystalclear low cost isa audio system tm 22 hw config. byte 10: fm volume scaling, default = 00100000 d7 d6 d5 d4 d3 d2 d1 d0 res fms2 fms1 fms0 res res res res fms2-fms0 fm volume scaling relative to wave- table digital input. these bits set the default fm volume level relative to the cs9236 wavetable interface port. once initialized, these bits can be controlled through x19. these bits are provided for backwards com- patibility with previous chips. 010 - 0 db 011 - +6 db 100 - -12 db 101 - -6 db 110 - +12 db 111 - +18 db hw config. byte 14: mono & dsp port control, default = 10000000 d7 d6 d5 d4 d3 d2 d1 d0 mim res res res sf1 sf0 spe mia this register sets the power up defaults for these fea- tures. after power-up, i16 may be used to control the dsp serial port, and i26 may be used to control the mono input. mia mono input attenuate. when set, the min input is attenuated 9 db. when clear, the min volume is 0 db. spe dsp serial port enable. when set, the dsp serial port is enabled. sf1,0 dsp serial port format. selects the format of the serial port once en- abled by spe. see the dsp serial audio data port section for more de- tails. 00 - 64-bit enhanced. 01 - 64 bit. 10 - 32 bit. 11 - adc/dac. mim mono in mute. when set, the min analog input is muted. when clear, min is mixed into the output mixer at a level set by mia. hw config. byte 15: e 2 prom checksum default = xxxxxxxx d7 d6 d5 d4 d3 d2 d1 d0 ec7 ec6 ec5 ec4 ec3 ec2 ec1 ec0 ec7-ec0 e 2 prom checksum byte. starts with the first byte of the size (after 55h/bbh) and ends with the last pro- grammed byte of the e 2 prom. only valid if eecs in hardware configura- tion byte 16 is set. hw config. byte 16: global config. byte 2 default = 00000000 d7 d6 d5 d4 d3 d2 d1 d0 res eecs aux1r 3den dspd1 psh res res this register sets the power up defaults for these fea- tures. after power-up, x18 may be used to control all bits except eecs. psh playback sample hold. when set, the last sample is held in dac1 when pen is cleared. when clear, zero is sent to dac1 when pen is cleared. dspd1 dsp port controls dac1. when set, the serial dsp port controls dac1 in- stead of the isa playback fifo. 3den 3d sound enable. when set, 3d sound is enabled on l/rout. aux1r aux1 remap. when set, writes to i18/19 (dac2 volume) also control the aux1 volume. when clear, i18/19 control dac2 volume and i2/3 control aux1 volume. this bit provides some backwards compatibil- ity when aux1 analog inputs are substituted for line analog inputs which are no longer available. eecs eeprom checksum. if set, indicates that hardware configuration byte 15 is a checksum for the entire eeprom (starting after 55h/bbh). ds252pp2 CS4235 crystalclear low cost isa audio system tm 23 hw config. byte 17: cdbase address length, default = 00000100 d7 d6 d5 d4 d3 d2 d1 d0 cal7 cal6 cal5 cal4 cal3 cal2 cal1 cal0 cal7-cal0 cdbase address length. determines the address length decode for the primary cdrom address, cdbase. cdbase must be on the same para- graph boundry as the address lengh decode. 00000001 - cdcs low for 1 byte 00000010 - cdcs low for 2 bytes 00000100 - cdcs low for 4 bytes 00001000 - cdcs low for 8 bytes 00010000 - cdcs low for 16 bytes 00100000 - cdcs low for 32 bytes 01000000 - cdcs low for 64 bytes 10000000 - cdcs low for 128 bytes xxx - all others, reserved bytes 19 through 21 map the interrupt number to the actual interrupt pins a - f. as shown in ta- ble 2, the byte 20 default is 0xb9; therefore, irq c, which is the lower nibble, maps to the isa interrupt 9. likewise irq d, which is the upper nibble, maps to the isa interrupt 11 (0bh). byte 22 maps the dma channel number to the actual dma pins a and b. as shown in the ta- ble, the byte 22 default is 0x10; therefore, drqa/ dacka is the lower nibble which maps to the isa dma channel 0. likewise drqb/ dackb is the upper nibble which maps to the isa dma channel 1. byte 23 maps dma c and irq g. the lower nibble maps dma c and defaults to dma 3. the upper nibble supports a seventh irq, irq g. the default is disabled (0), providing backwards compatibility with other cirrus audio parts. if irq g is connected to an isa interrupt (typically 10), then this byte must be modified to reflect the hardware connection. hostload procedure this procedure is provided for backwards com- patibility with the cs4236. since the e 2 prom allows all resource and firmware patch data to be loaded at power-up, this procedure is typically only used with motherboard devices that do not include an e 2 prom. to download pnp resource data from the host to the parts internal ram, use the following sequence: 1. configure control i/o base address, ctrlbase, by one of two methods: regular pnp cycle or crystal key method. a. the host can use the regular pnp cycle to program the ctrlbase, and then place the chip in the wait_for_key_state b. if the crystal key method is used: first, send the 32-byte crystal key to i/o address port (ap). second, configure logical device 2 base address, ctrlbase, by writing to ap (15h, 02h, 47h, xxh, xxh, 33h, 01h, 79h). note: the two xxh represent the base_ad- dress_high and base_address_low respectively. the default is: 01h, 20h. 2. write 57h (jump to rom) command to ctrlbase+5. 3. download the pnp resource data. a. send download command by writing aah to ctrlbase+5. b. send starting download address (4000h) by writing low byte (00h) first, and then high byte (40h) to ctrlbase+5. c. send the hardware configuration and re- source data in successive bytes to ctrlbase+5. this includes the hardware configuration and the pnp resource data. ds252pp2 CS4235 crystalclear low cost isa audio system tm 24 the pnp resource format is described in the pnp data section. the resource header should not contain the first four bytes which are only used for e 2 prom loads. d. end download by writing 00h to ctrlbase+6. 4. download firmware data. contact cirrus logic for the bios kit which gives examples of how to download firmware. 5. if any of the hardware configuration data (first 19 bytes) has changed, 5ah must be written to ctrlbase+5 to force the part to internally update this information. the new pnp data is loaded and the part is ready for the next pnp cycle. external e 2 prom the plug and play specification defines 32 bits of the 72-bit serial identifier as being a user de- fined serial number. the e 2 prom is used to change the user section of the identifier, store default resource data for pnp, hardware con- figuration data specific to the CS4235, and firmware patches to upgrade the core processor functionality. the e 2 prom interface uses an industry standard 2-wire interface consisting of a bi-directional data line and a clock line driven from the part. after power-on the part looks for the existence of an e 2 prom device and loads the user de- fined data. the existence is determined by the first two bytes read (0x55 followed by 0xbb). if the first two bytes are correct, the part reads the next two bytes to determine the length of data in the e 2 prom. the length bytes indicate the number of bytes left to be read (not including the two validation bytes or two length bytes). as shown in figure 3, the e 2 prom is read using a start bit followed by a dummy write, to initialize the address to zero. then another start bit and device address, followed by all the data. since the part uses the sequential read properties of the e 2 prom, only one e 2 prom, is supported (ganged e 2 proms are not supported). some e 2 proms that are compatible with this interface are: atmel at24cxx series microchip 24lcxxb series national nm24cxxl series ramtron fm24cxx series sgs thompson st24cxx series xicor x24cxx series where the xx is replaced by 02, 04, 08, or 16 based on the size of the e 2 prom desired. the size of 08 (1k bytes) is preferred since it allows the maximum flexibility for upgrading firmware patches. other e 2 proms compatible with fig- ure 3 and the timing parameters listed in the front of the data sheet may also be used. the maximum hardware configuration and pnp resource ram data supported is 384 bytes, and a four byte header; therefore, the maximum amount of data storage, without firmware patches, in e 2 prom would be 388 bytes. the maximum size e 2 prom needed is 770 bytes, to allow the inclusion of firmware patches after the pnp resource data. if an external e 2 prom exists, it is accessed by the serial interface and is connected to the sda and scl pins. the two-wire interface is control- led by three bits in the control logical device, hardware control register (ctrlbase+1). the serial data can be written to or read from the e 2 prom by sequentially writing or reading that register. the three register bits, d0, d1, d2 are labeled clk, dout, and din/een respectively. the din/een bit, when written to a one, en- ables the e 2 prom serial interface. when the din/een bit is written to a zero, the serial inter- face is disabled. the din/een bit is also the data in (din) signal to read back data from the e 2 prom. the sda pin is a bi-directional open- ds252pp2 CS4235 crystalclear low cost isa audio system tm 25 drain data line supporting din and dout; therefore, to read the correct data, the dout bit must be set to a one prior to performing a read of the register. otherwise, the data read back from din/een will be all zeros. the e 2 prom data can then be read from the din/een bit. the clk bit timing is controlled by the host software. this is the serial clock for the e 2 prom output on the scl pin. the dout bit is used to write/program the data out to the e 2 prom. an external pull-up resistor is re- quired on sda because it is an open-drain output. use the guidelines in the specific e 2 prom data sheet to select the value of the pull-up resistor (a typical value would be 3.3 k w ). programming the e 2 prom: 1. configure control i/o base address by one of two methods: regular pnp cycle or crystal key method. a. the host can use the regular pnp cycle to program the logical device 2 i/o base ad- dress, and then place the chip in the wait_for_key_state b. if the crystal key method is used: first, write to the ap, send the 32-byte crystal key. second, configure the control i/o base address by writing 15h, 02h, 47h, 01h, 20h, 33h, 01h, 79h to the ap. 2. refer to the specific data sheet for the e 2 prom you are using for timing require- ments and data format. also, refer to the loading resource data section of this data sheet for the e 2 prom resource data format. 3. send the e 2 prom data in successive bits to ctrlbase+1 (hardware control register) while following the e 2 prom data sheet for- mat. the e 2 prom now contains the pnp resource data. for this new data to take effect, the part must be reset, causing the part to read the e 2 prom during initialization. cirrus can pro- vide a utility, resource.exe, to program e 2 proms through the control logical device in- terface. windows sound system codec the wss codec software interface consists of 4 i/o locations starting at the plug and play ad- dress wssbase, and supports 12-bit address decoding. if the upper address bits, sa12-sa15 are used, they must be 0 to decode a valid ad- dress. the wss codec also requires one interrupt and one or preferably two dma chan- nels, one for playback and one for capture. since the wss codec and sound blaster device are mutually exclusive, the two devices share the same interrupt and dma playback channel. the wss functions include stereo analog-to- digital and digital-to-analog converters (adcs and dacs), analog mixing, anti-aliasing and re- construction filters, line and microphone level s 10100000 a 00000000 a s 10100001 a data data p 1 a start part address start acknowledge no acknowledge stop acknowledge data eeprom write read bank address part address crystal ic figure 3. eeprom format ds252pp2 CS4235 crystalclear low cost isa audio system tm 26 inputs, simultaneous capture and playback (at in- dependent sample frequencies) and a parallel bus interface. enhanced functions (modes) the initial state is labeled mode 1 and forces the part to appear as a cs4248. the more popu- lar second mode, mode 2, forces the part to appear as a cs4231 super set and is compatible with the cs4232. to switch from mode 1 to mode 2, the cms1,0 bits, in the mode and id register (i12), should be set to 10 respec- tively. when mode 2 is selected, the bit ia4 in the index address register (r0) will be decoded as a valid index pointer providing 16 additional registers and increased functionality over the cs4248. to reverse the procedure, set the cms1,0 bits to 00 and the part will resume operation in mode 1. except for the capture data format (i28), capture base count (i30/31), and alter- nate feature status (i24) registers, all other mode 2 functions retain their values when re- turning to mode 1. mode 3 is selected by setting cms1,0 to 11. mode 3 allows access to a third set of "ex- tended registers" which are designated x0-x31. the extended registers are accessed through i23. the additional mode 3 functions are: 1. a full symmetrical mixer. this changes the in- put multiplexer to a input mixer. 2. independent sample frequency control on the adcs and dacs. 3. programmable gain and attenuation on the microphone inputs. fifos the wss codec contains 16-sample fifos in both the playback and capture digital audio data paths. the fifos are transparent and have no programming associated with them. when playback is enabled, the playback fifo continually requests data until the fifo is full, and then makes requests as positions inside the fifo are emptied, thereby keeping the playback fifo as full as possible. thus when the system cannot respond within a sample period, the fifo starts to empty, avoiding a momentary loss of audio data. if the fifo runs out of data, the last valid sample can be continuously output to the dacs (if dacz in i16 is clear) which will eliminate pops from occurring. when capture is enabled, the capture fifo tries to continually stay empty by making requests every sample period. thus when the system can- not respond within a sample period, the capture fifo starts filling, thereby avoiding a loss of data in the audio data stream. wss codec pio register interface four i/o mapped locations are available for ac- cessing the codec functions and mixer. the control registers allow access to status, audio data, and all indirect registers via the index reg- isters. the ior and iow signals are used to define the read and write cycles respectively. a pio access to the codec begins when the host puts an address on to the isa bus which matches wssbase and drives aen low. wssbase is pro- grammed during a plug and play configuration sequence. once a valid base address has been decoded then the assertion of ior will cause the wss codec to drive data on the isa data bus lines. write cycles require the host to assert data on the isa data bus lines and strobe the iow signal. the wss codec will latch data into the pio register on the rising edge of the iow strobe. ds252pp2 CS4235 crystalclear low cost isa audio system tm 27 the audio data interface typically uses dma re- quest/grant pins to transfer the digital audio data between the wss codec and the bus. the wss codec is responsible for asserting a request sig- nal whenever the codecs internal buffers need updating. the bus responds with an acknowledge signal and strobes data to and from the codec, 8 bits at a time. the wss codec keeps the re- quest pin active until the appropriate number of 8-bit cycles have occurred to transfer one audio sample. note that different audio data types will require a different number of 8-bit transfers. dma interface the second type of parallel bus cycle from the wss codec is a dma transfer. dma cycles are distinguished from pio register cycles by the as- sertion of a drq followed by an acknowledgment by the host by the assertion of dack (with aen high). while the acknow- ledgment is received from the host, the wss codec assumes that any cycles occurring are dma cycles and ignores the addresses on the address lines. the wss codec may assert the dma request signal at any time. once asserted, the dma re- quest will remain asserted until a complete dma cycle occurs to the part. dma transfers may be terminated by resetting the pen and/or cen bits in the interface configuration register (i9), de- pending on the dma that is in progress (playback, capture, or both). termination of dma transfers may only happen between sample transfers on the bus. if drq goes active while resetting pen and/or cen, the request must be acknowledged with dack and a final sample transfer completed. dma channel mapping mapping of the wss codecs drq and dack onto the isa bus is accomplished by the plug and play configuration registers. if the plug and play resource data specifies only one dma channel for the codec (or the codec is placed in sdc mode) then both the playback and capture dma requests should be routed to the same drq/ dack pair (dma channel select 0). if the plug and play resource data specifies two dma channels for the codec, then the playback dma request will be routed to the dma pair specified by the dma channel select 0 resource data, and the capture dma requests will be routed to the dma pair specified by the dma channel select 1 resource data. dual dma channel mode the wss codec supports a single and a dual dma channel mode. in dual dma channel mode, playback and capture dma requests and acknowledges occur on independent dma chan- nels. in dual dma mode, sdc should be set to 0. the playback- and capture-enables (pen, cen, i9) can be changed without a mode change enable (mce, r0). this allows for proper full duplex control where applications are independently using playback and capture. single dma channel (sdc) mode when two dma channels are not available, the sdc mode forces all dma transfers (capture or playback) to occur on a single dma channel (playback channel). the trade-off is that the wss codec will no longer be able to perform simultaneous dma capture and playback. to enable the sdc mode, set the sdc bit in the interface configuration register (i9). with the sdc bit asserted, the internal workings of the wss codec remain exactly the same as dual mode, except for the manner in which dma re- quest and acknowledges are handled. the playback of audio data will occur on the playback channel exactly as dual channel opera- tion; however, the capture audio channel is now diverted to the playback channel. alternatively stated, the capture dma request occurs on dma channel select 0 for the wss codec. (in modes 2 and 3, the capture data format is al- ds252pp2 CS4235 crystalclear low cost isa audio system tm 28 ways set in register i28.) if both playback and capture are enabled, the default will be playback. sdc does not have any affect when using pio accesses. sound system codec register interface the windows sound system codec is mapped via four locations. the i/o base address, wssbase, is determined by the plug and play configuration. the wssbase supports four direct registers, shown in table 3. the first two direct registers are used to access 32 indirect registers shown in table 4. the index address register (wssbase+0) points to the indirect register that is accessed through the indexed data register (wssbase+1). this section describes all the direct and indirect registers for the wss codec. table 5 details a summary of each bit in each register with ta- bles 6 through 10 illustrating the majority of decoding needed when programming the wss logical device, and are included for reference. when enabled, the wss codec default state is defined as mode 1. mode 1 is backwards compatible with the cs4248 and only allows ac- cess to the first 16 indirect registers. putting the part in mode 2 or mode 3, using cms1,0 bits in the mode and id register (i12), allows ac- cess to indirect registers 16 through 31. putting the part in mode 3 also allows access to the extended registers through i23 and other ex- tended features in the indirect registers. direct registers: (r0-r3) address reg. register name wssbase+0 r0 index address register wssbase+1 r1 indexed data register wssbase+2 r2 status register wssbase+3 r3 pio data register table 3. wss codec direct register index register name i0 left analog loopback i1 right analog loopback i2 left aux #1 volume i3 right aux #1 volume i4 left aux #2 volume i5 right aux #2 volume i6 left dac1 volume i7 right dac1 volume i8 fs & playback data format i9 interface configuration i10 pin control i11 error status and initialization i12 mode and id i13 reserved i14 playback upper base count i15 playback lower base count i16 alternate feature enable i i17 alternate feature enable ii i18 left dac2 volume i19 right dac2 volume i20 control/ram access i21 ram access end i22 alternate sample frequency i23 extended register access (x regs) i24 alternate feature status i25 compatibility id i26 mono input control i27 left master output volume i28 capture data format i29 right master output volume i30 capture upper base count i31 capture lower base count table 4. wss codec indirect registers ds252pp2 CS4235 crystalclear low cost isa audio system tm 29 direct mapped registers the first two wss codec registers provide indi- rect accessing to more codec registers via an index register. the other two registers provide status information and allow audio data to be transferred to and from the wss codec without using dma cycles or indexing. note that register defaults are listed in binary form with reserved bits marked with x to indi- cate unknown. bits in the default marked with an e indicate that the bit is initialized through e 2 prom. to maintain compatibility with future parts, these reserved bits must be written as 0, and must be masked off when the register is read. the current value read for reserved bits is not guaranteed on future revisions. while the re- served bits are listed as "res" in the bit position, "rbc" is used for "reserved, backwards compat- ible" for bits that were used on previous chips, but are no longer required on this chip. these bits are read/writable but should generally be set to 0 for backwards compatibility. index address register (wssbase+0, r0) d7 d6 d5 d4 d3 d2 d1 d0 init mce trd ia4 ia3 ia2 ia1 ia0 ia3-ia0 index address: these bits define the address of the indirect register ac- cessed by the indexed data register (r1). these bits are read/write. ia4 allows access to indirect registers 16 - 31. in mode 1, this bit is re- served and must be written as zero. trd transfer request disable: this bit, when set, causes dma transfers to cease when the int bit of the status register (r2) is set. independent for playback and capture interrupts. 0 - transfers enabled (playback and capture drqs occur uninhibited) 1 - transfers disabled (playback and capture drq only occur if int bit is 0) mce mode change enable: this bit must be set whenever the current mode of the wss codec is changed. the data format (i8, i28) and interface configuration (i9) registers cannot be changed unless this bit is set. the exceptions are cen and pen which can be changed "on-the-fly". the dac output is muted when mce is set. init wss codec initialization: this bit is read as 1 when the codec is in a state in which it cannot respond to parallel interface cycles. this bit is read-only. immediately after reset (and once the wss codec has left the init state), the state of this register is: 010x0000 (binary - where x indi- cates unknown). during initialization and software power down (pdwn in ctrlbase+7), this register cannot be written and always reads 10000000 (80h) indexed data register (wssbase+1, r1) d7 d6 d5 d4 d3 d2 d1 d0 id7 id6 id5 id4 id3 id2 id1 id0 id7-id0 indexed data register: these bits are the indirect register referenced by the indexed address register (r0). ds252pp2 CS4235 crystalclear low cost isa audio system tm 30 status register (wssbase+2, r2, read only) d7 d6 d5 d4 d3 d2 d1 d0 cu/ lcl/ r crdy ser pu/ lpl/ r prdy int int interrupt status: this indicates the status of the internal interrupt logic of the wss codec. this bit is cleared by any write of any value to this register. the ien bit of the pin control register (i10) determines whether the state of this bit is re- flected on the irq pin assigned to the wss codec. read states 0 - interrupt inactive 1 - interrupt active prdy playback data ready. the playback data register (r3) is ready for more data. this bit would be used when di- rect programmed i/o data transfers are desired. 0 - data still valid. do not overwrite. 1 - data stale. ready for next host data write value. pl/ r playback left/right sample: this bit indicates whether data needed is for the left channel or right channel. 0 - right needed 1 - left or mono needed pu/ l playback upper/lower byte: this bit indicates whether the playback data needed is for the upper or lower byte of the channel. 0 - lower needed 1 - upper or 8-bit needed ser sample error: this bit indicates that a sample was not serviced in time and an error has occurred. the bit indi- cates an overrun for capture and underrun for playback. if both the capture and playback are enabled, the source which set this bit can not be determined. however, the alter- nate feature status register (i24) indicates the exact source of error. crdy capture data ready. the capture data register (r3) contains data ready for reading by the host. this bit would be used for direct pro- grammed i/o data transfers. 0 - data is stale. do not reread the information. 1 - data is fresh. ready for next host data read. cl/ r capture left/right sample: this bit indicates whether the capture data waiting is for the left channel or right channel. 0 - right 1 - left or mono cu/ l capture upper/lower byte: this bit indicates whether the capture data ready is for the upper or lower byte of the channel. 0 - lower available 1 - upper or 8-bit available note on prdy/crdy: these two bits are de- signed to be read as one when action is required by the host. for example, when prdy is set to one, the device is ready for more data; or when the crdy is set to one, data is available to the host. the definition of the crdy and prdy bits are therefore consistent in this regard. i/o data registers the pio data register is two registers mapped to the same address. writes to this register sends data to the playback data register. reads from this register will receive data from the capture data register. ds252pp2 CS4235 crystalclear low cost isa audio system tm 31 capture i/o data register (wssbase+3, r3, read only) d7 d6 d5 d4 d3 d2 d1 d0 cd7 cd6 cd5 cd4 cd3 cd2 cd1 cd0 cd7-cd0 capture data port. this is the control register where capture data is read during programmed i/o data trans- fers. the reading of this register will increment the state machine so that the following read will be from the next appropriate byte in the sample. the exact byte which is next to be read can be determined by reading the status register (r2). once all relevant bytes have been read, the state machine will point to the last byte of the sample until a new sample is received from the adcs. once the status register (r2) is read and a new sample is received from the fifo, the state ma- chine and status register (r2) will point to the first byte of the new sample. during initialization and software power down of the wss codec, this register can not be written and is always read 10000000 (80h) playback i/o data register wssbase+3, r3, write only) d7 d6 d5 d4 d3 d2 d1 d0 pd7pd6pd5pd4pd3pd2pd1pd0 pd7-pd0 playback data port. this is the control register where playback data is written during programmed io data transfers. writing data to this register will increment the playback byte tracking state machine so that the following write will be to the correct byte of the sample. once all bytes of a sample have been written, subsequent byte writes to this port are ignored. the state machine is reset after the status register (r2) is read, and the current sam- ple is sent to the dacs via the fifos. indirect mapped registers these registers are accessed by placing the ap- propriate index in the index address register (r0) and then accessing the indexed data regis- ter (r1). a detailed description of each indirect register is given below. all reserved bits should be written zero and may be 0 or 1 when read. note that indirect registers 16-31 are not avail- able when in mode 1 (cms1,0 in mode and id register i12 are both zero). left analog loopback (i0) default = 000xxxxx d7 d6 d5 d4 d3 d2 d1 d0 lss1 lss0 mge res rbc rbc rbc rbc mge this bit controls the 20 db gain boost for the mic analog input. lss1-lss0 left output loopback. setting these bits to 11 enables the left output loopback into the input mixer. bit combinations of 01, 10, and 00 dis- able the loopback. right analog loopback(i1) default = 000xxxxx d7 d6 d5 d4 d3 d2 d1 d0 rss1 rss0 mge res rbc rbc rbc rbc mge this bit is identical to the mge bit in i0. it controls the 20 db gain boost for the mic analog input. rss1-rss0 right output loopback. setting these bits to 11 enables the right output loopback into the input mixer. other bit combinations disable the loop- back. ds252pp2 CS4235 crystalclear low cost isa audio system tm 32 left auxiliary #1 volume (i2) default = 11x00000 d7 d6 d5 d4 d3 d2 d1 d0 lx1om lx1im rbc lx1g4 lx1g3 lx1g2 lx1g1 lx1g0 note: although this register generally controls the vol- ume for laux1, the laux1 volume can be controlled through i18 by setting aux1r in x18. lx1g4-lx1g0 left auxiliary #1, laux1, mix gain. the least significant bit represents 1.5 db, with 01000 = 0 db. see table 8. lx1im left auxiliary #1 mute. when set, the left auxiliary #1 input, laux1, to the input mixer is muted. lx1om left auxiliary #1 mute. when set to 1, the left auxiliary #1 input, laux1, to the output mixer is muted. right auxiliary #1 volume (i3) default = 11x00000 d7 d6 d5 d4 d3 d2 d1 d0 rx1om rx1im rbc rx1g4 rx1g3 rx1g2 rx1g1 rx1g0 note: although this register generally controls the volume for raux1, the raux1 volume can be con- trolled through i19 by setting aux1r in x18. rx1g4-rx1g0 right auxiliary #1, raux1, mix gain. the least significant bit represents 1.5 db, with 01000 = 0 db. see table 8. rx1im right auxiliary #1 mute. when set to 1, the right auxiliary #1 input, raux1, to the input mixer is muted. rx1om right auxiliary #1 mute. when set to 1, the right auxiliary #1 input, raux1, to the output mixer is muted. left auxiliary #2 volume (i4) default = 11x00000 d7 d6 d5 d4 d3 d2 d1 d0 lx2om lx2im res lx2g4 lx2g3 lx2g2 lx2g1 lx2g0 lx2g4-lx2g0 left auxiliary #2, laux2, mix gain. the least significant bit represents 1.5 db, with 01000 = 0 db. see table 8. lx2im left auxiliary #2 mute. when set to 1, the left auxiliary #2 input, laux2, to the input mixer is muted. lx2om left auxiliary #2 mute. when set to 1, the left auxiliary #2 input, laux2, to the output mixer is muted. right auxiliary #2 volume (i5) default = 11x00000 d7 d6 d5 d4 d3 d2 d1 d0 rx2om rx2im res rx2g4 rx2g3 rx2g2 rx2g1 rx2g0 rx2g4-rx2g0 right auxiliary #2, raux2, mix gain. the least significant bit represents 1.5 db, with 01000 = 0 db. see table 8. rx2im right auxiliary #2 mute. when set, the right auxiliary #2 input, raux2, to the input mixer is muted. rx2om right auxiliary #2 mute. when set, the right auxiliary #2 input, raux2, to the output mixer is muted. left dac1 volume (i6) default = 10000111 d7 d6 d5 d4 d3 d2 d1 d0 ld1om res ld1a5 ld1a4 ld1a3 ld1a2 ld1a1 ld1a0 ld1a5-ld1a0 left dac1 attenuation. the least significant bit represents -1.5 db, with 000000 = 0 db. the total range is 0 to -94.5 db. see table 6. ld1om left dac1 output mute. when set, the left dac1 to the output mixer is muted. ds252pp2 CS4235 crystalclear low cost isa audio system tm 33 indirect registers: (i0-i31) ia4-ia0 d7d6d5d4d3d2d1d0 0 lss1lss0mge----- 1 rss1rss0mge----- 2 lx1om lx1im - lx1g4 lx1g3 lx1g2 lx1g1 lx1g0 3 rx1om rx1im - rx1g4 rx1g3 rx1g2 rx1g1 rx1g0 4 lx2om lx2im - lx2g4 lx2g3 lx2g2 lx2g1 lx2g0 5 rx2om rx2im - rx2g4 rx2g3 rx2g2 rx2g1 rx2g0 6 ld1om - ld1a5 ld1a4 ld1a3 ld1a2 ld1a1 ld1a0 7 rd1om - rd1a5 rd1a4 rd1a3 rd1a2 rd1a1 rd1a0 8 - 16b - s/ m cfs2 cfs1 cfs0 c2sl 9 cpio ppio - cal1 cal0 sdc cen pen 10 xctl1 xctl0 osm1 osm0 den dtm ien - 11 cor pur aci drs orr1 orr0 orl1 orl0 12 1 cms1 cms0 - 1 0 1 0 13 -------- 14 pub7 pub6 pub5 pub4 pub3 pub2 pub1 pub0 15 plb7 plb6 plb5 plb4 plb3 plb2 plb1 plb0 16 - - cmce pmce sf1 sf0 spe dacz 17 test test test test - - - hpf 18 ld2om ld2im - ld2a4 ld2a3 ld2a2 ld2a1 ld2a0 19 rd2om rd2im - rd2a4 rd2a3 rd2a2 rd2a1 rd2a0 20 cr7 cr6 cr5 cr4 cr3 cr2 cr1 cr0 21 re7 re6 re5 re4 re3 re2 re1 re0 22 sre div5 div4 div3 div2 div1 div0 cs2 23 xa3 xa2 xa1 xa0 xrae xa4 - - 24 - - ci pi cu co po pu 25 00000011 26 mim - - - mia3 mia2 mia1 mia0 27 lom los1 los0 log4 log3 log2 log1 log0 28 - 16b - s/ m- - - - 29 rom ros1 ros0 rog4 rog3 rog2 rog1 rog0 30 cub7 cub6 cub5 cub4 cub3 cub2 cub1 cub0 31 clb7 clb6 clb5 clb4 clb3 clb2 clb1 clb0 table 5. wss codec direct & indirect register bits direct registers: wssbase (r0-r3) address d7 d6 d5 d4 d3 d2 d1 d0 wssbase+0 r0 init mce trd ia4 ia3 ia2 ia1 ia0 wssbase+1 r1 id7 id6 id5 id4 id3 id2 id1 id0 wssbase+2 r2 cu/ lcl/ r crdy ser pu/ lpl/ r prdy int wssbase+3 r3 cd7/pd7 cd6/pd6 cd5/pd5 cd4/pd4 cd3/pd3 cd2/pd2 cd1/pd1 cd0/pd0 ds252pp2 CS4235 crystalclear low cost isa audio system tm 34 a5 a4 a3 a2 a1 a0 level 0 0 0 0 0 0 0 0.0 db 1000001-1.5 db 2000010-3.0 db 3000011-4.5 db ....... . 8001000-12.0 db ....... . ....... . 60 1 1 1 1 0 0 -90.0 db 61 1 1 1 1 0 1 -91.5 db 62 1 1 1 1 1 0 -93.0 db 63 1 1 1 1 1 1 -94.5 db table 6. dac1 cfs 21 0 c2sl = 0 c2sl=1 0 0 0 8.0 khz 5.51 khz 0 0 1 16.0 khz 11.025 khz 0 1 0 27.42 khz 18.9 khz 0 1 1 32.0 khz 22.05 khz 1 0 0 n/a 37.8 khz 1 0 1 n/a 44.1 khz 1 1 0 48.0 khz 33.075 khz 1 1 1 9.6 khz 6.62 khz table 7. i8 sample frequency selection g4 g3 g2 g1 g0 level 0 0 0 0 0 0 12.0 db 1 0 0 0 0 1 10.5 db 2000109.0 db 3000117.5 db 4001006.0 db 5001014.5 db 6001103.0 db 7001111.5 db 8010000.0 db 901001-1.5 db 1001010-3.0 db 1101011-4.5 db 1201100-6.0 db ...... . ...... . ...... . 2411000-24.0 db 2511001-25.5 db 2611010-27.0 db 2711011-28.5 db 2811100-30.0 db 2911101-31.5 db 3011110-33.0 db 3111111muted table 8. aux1, aux2, dac2 g4 g3 g2 g1 g0 master mic 0 0 0 0 0 0 6 db 22.5 db 1 0 0 0 0 1 4 db 21.0 db 2 0 0 0 1 0 2 db 19.5 db 3 00011 0 db 18.0 db 4 0 0 1 0 0 -2 db 16.5 db . ..... . . 12 0 1 1 0 0 -18 db 4.5 db 13 0 1 1 0 1 -20 db 3.0 db 14 0 1 1 1 0 -22 db 1.5 db 15 0 1 1 1 1 -24 db 0 db . ..... . . 28 1 1 1 0 0 -50 db -19.5 db 29 1 1 1 0 1 -52 db -21.0 db 30 1 1 1 1 0 -54 db -22.5 db 31 1 1 1 1 1 -56 db muted note: master volume is also affected by l/rs1, l/rs0 mic volume assumes that boost is off (mbst=0). table 9. master and microphone volume decimal value adc fs (khz) adc divider dac fs (khz) dac divider 0 50.40 16 x 21 50.40 16 x 21 1 48.00 353 48.00 353 2 32.00 529 32.00 529 3 27.42 617 27.42 617 4 16.00 1058 16.00 1058 59.600 1764 9.600 1764 68.000 2117 8.000 2117 76.620 2558 6.620 2558 8 50.40 16 x 21 50.40 16 x 21 .. . . . 21 50.40 16 x 21 50.40 16 x 21 22 48.10 16 x 22 48.10 16 x 22 23 46.01 16 x 23 46.01 16 x 23 24 44.10 16 x 24 44.10 16 x 24 25 42.36 16 x 25 42.36 16 x 25 26 40.70 16 x 26 40.70 16 x 26 .. . . . 189 5.600 16 x 189 5.600 16 x 189 190 5.570 16 x 190 5.570 16 x 190 191 5.541 16 x 191 5.541 16 x 191 192 5.512 16 x 192 5.512 16 x 192 193 5.512 16 x 192 5.483 16 x 193 194 5.512 16 x 192 5.455 16 x 194 .. . . . 255 5.512 16 x 192 4.150 16 x 255 table 10. x12/13 sample frequency selection ds252pp2 CS4235 crystalclear low cost isa audio system tm 35 right dac1 volume (i7) default = 10000111 d7 d6 d5 d4 d3 d2 d1 d0 rd1om res rd1a5 rd1a4 rd1a3 rd1a2 rd1a1 rd1a0 rd1a5-rd1a0 right dac1 attenuation. the least significant bit represents -1.5 db, with 000000 = 0 db. the total range is 0 to -94.5 db. see table 6. rd1om right dac1 mute. when set, the right dac1 to the output mixer is muted. fs and playback data format (i8) default = 00000000 d7 d6 d5 d4 d3 d2 d1 d0 rbc16brbcs/ m cfs2 cfs1 cfs0 c2sl c2sl clock 2 source select: this bit selects the clock base used for the audio sample rates for both capture and playback. note that this bit can be disabled by setting sre in i22 or by setting ifse in x11. caution: c2sl can only be changed while mce (r0) is set. cfs2-cfs0 clock frequency divide select: these bits select the audio sample fre- quency for both capture and playback. the actual audio sample frequency depends on which clock base (c2sl) is selected. note that these bits can be disabled by setting sre in i22 or ifse in x11. caution: cfs2-cfs0 can only be changed while mce (r0) is set. divide c2sl = 0 c2sl = 1 0 - 3072 8.0 khz 5.51 khz 1 - 1536 16.0 khz 11.025 khz 2 - 896 27.42 khz 18.9 khz 3 - 768 32.0 khz 22.05 khz 4 - 448 n/a 37.8 khz 5 - 384 n/a 44.1 khz 6 - 512 48.0 khz 33.075 khz 7 - 2560 9.6 khz 6.62 khz s/ m stereo/mono select: this bit deter- mines how the audio data streams are formatted. selecting stereo will result in alternating samples repre- senting left and right audio channels. mono playback plays the same audio sample on both channels. mono capture only captures data from the left channel. in mode 1, this bit is used for both playback and capture. in modes 2 and 3, this bit is only used for playback, and the capture format is independently se- lected via i28. mce (r0) or pmce (i16) must be set to modify s/ m. see changing audio data formats section for more details. 0 - mono 1 - stereo 16b selects between 8-bit unsigned and 16-bit signed data for playback. the capture format is independently se- lected via register i28. mce (r0) or pmce (i16) must be set to modify the upper four bits of this register. see changing audio data formats section for more details. 0 - 8-bit unsigned data 1 - 16-bit signed data interface configuration (i9) default = 00x00100 d7 d6 d5 d4 d3 d2 d1 d0 cpio ppio res cal1 cal0 sdc cen pen pen playback enable. this bit enables playback. the wss codec will generate a drq and respond to dack signal when this bit is en- abled and ppio=0. if ppio=1, pen enables pio playback mode. pen may be set and reset without setting the mce bit. 0 - playback disabled (playback drq and pio inactive) 1 - playback enabled ds252pp2 CS4235 crystalclear low cost isa audio system tm 36 cen capture enabled. this bit enables the capture of data. the wss codec will generate a drq and respond to dack signal when cen is enabled and cpio=0. if cpio=1, cen en- ables pio capture mode. cen may be set and reset without setting the mce bit. 0 - capture disabled (capture drq and pio inactive) 1 - capture enabled sdc single dma channel: this bit will force both capture and playback dma requests to occur on the play- back dma channel. this bit forces the wss codec to use one dma channel. should both capture and playback be enabled in this mode, only the playback will occur. see the dma interface section for further ex- planation. 0 - dual dma channel mode 1 - single dma channel mode cal1,0 calibration: these bits determine which type of calibration the wss codec performs whenever the mode change enable (mce) bit, r0, changes from 1 to 0. the number of sample periods required for calibra- tion is listed in parenthesis. 0 - no calibration (0) 1 - converter calibration (321) 2 - dac calibration (120) 3 - full calibration (450) ppio playback pio enable: this bit deter- mines whether the playback data is transferred via dma or pio. 0 - dma transfers 1 - pio transfers cpio capture pio enable: this bit deter- mines whether the capture data is transferred via dma or pio. 0 - dma transfers 1 - pio transfers caution: this register, except bits cen and pen, can only be written while in mode change enable (either mce or pmce). see the chang- ing sampling rate section for more details. pin control (i10) default = 0000000x d7 d6 d5 d4 d3 d2 d1 d0 xctl1 xctl0 osm1 osm0 den dtm ien res ien interrupt enable: this bit enables the interrupt pin. the interrupt pin will re- flect the value of the int bit of the status register (r2). the interrupt pin is active high. 0 - interrupt disabled 1 - interrupt enabled dtm dma timing mode. mode 2 & 3 only. when set, causes the current dma request signal to be deasserted on the rising edge of the iow or ior strobe during the next to last byte of a dma transfer. when dtm = 0 the dma request is released on the fall- ing edge of the iow or ior during the last byte of a dma transfer. den dither enable: when set, triangular pdf dither is added before truncating the adc 16-bit value to 8-bit, un- signed data. dither is only active in the 8-bit unsigned data mode. 0 - dither enabled 1 - dither disabled osm1-osm0 these bits are enabled by setting sre = 1 in i22. these bits in com- bination with div5-div0 and cs2 (i22) determine the current sample rate of the wss codec when sre = 1. note that these bits can be disabled by setting ifse in x11. 00 - 12 khz < fs 24 khz 01 - fs > 24 khz 10 - fs 12 khz 11 - reserved ds252pp2 CS4235 crystalclear low cost isa audio system tm 37 xctl1-xctl0 xctl control: these bits are reflected on the xctl1,0 pins of the part. note: xctl1 is multiplexed with other functions; therefore, it may not be available on a particular design. 0 - ttl logic low on xctl1,0 pins 1 - ttl logic high on xctl1,0 pins error status and initialization (i11, read only) default = 00000000 d7 d6 d5 d4 d3 d2 d1 d0 cor pur aci drs orr1 orr0 orl1 orl0 orl1-orl0 overrange left detect: these bits determine the overrange on the left adc channel. these bits are up- dated on a sample by sample basis. 0 - less than -1.5 db 1 - between -1.5 db and 0 db 2 - between 0 db and 1.5 db overrange 3 - greater than 1.5 db overrange orr1-orr0 overrange right detect: these bits determine the overrange on the right adc channel. 0 - less than -1.5 db 1 - between -1.5 db and 0 db 2 - between 0 db and 1.5 db overrange 3 - greater than 1.5 db overrange drs drq status: this bit indicates the current status of the drqs assigned to the wss codec. 0 - capture and playback drqs are presently inactive 1 - capture or playback drqs are presently active aci auto-calibrate in-progress: this bit indicates the state of calibration. 0 - calibration not in progress 1 - calibration is in progress pur playback underrun: this bit is set when playback data has not arrived from the host in time to be played. as a result, if dacz = 0, the last valid sample will be sent to the dacs. this bit is set when an error occurs and will not clear until the status register (r2) is read. cor capture overrun: this bit is set when the capture data has not been read by the host before the next sample arrives. the old sample will not be overwritten and the new sample will be ignored. this bit is set when an error condition occurs and will not clear until the status register (r2) is read. the ser bit in the status register (r2) is simply a logical or of the cor and pur bits. this enables a polling host cpu to detect an error condition while checking other status bits. mode and id (i12) default = 100x1010 d7 d6 d5 d4 d3 d2 d1 d0 1cms1cms0res1010 res reserved. must write 0. could read as 0 or 1. cms1,0 codec mode select bits: enables the extended registers and functions of the part. 00 - mode 1 01 - reserved 10 - mode 2 11 - mode 3 reserved (i13) default = xxxxxxxx d7 d6 d5 d4 d3 d2 d1 d0 rbc rbc rbc rbc rbc rbc res rbc rbc reserved, backwards compatible. res reserved. must write 0. could read as 0 or 1. ds252pp2 CS4235 crystalclear low cost isa audio system tm 38 playback upper base (i14) default = 00000000 d7 d6 d5 d4 d3 d2 d1 d0 pub7 pub6 pub5 pub4 pub3 pub2 pub1 pub0 pub7-pub0 playback upper base: this register is the upper byte which represents the 8 most significant bits of the 16-bit playback base register. reads from this register return the same value which was written. the current count registers cannot be read. when set for mode 1 or sdc, this register is used for both the play- back and capture base registers. playback lower base (i15) default = 00000000 d7 d6 d5 d4 d3 d2 d1 d0 plb7 plb6 plb5 plb4 plb3 plb2 plb1 plb0 plb7-plb0 lower base bits: this register is the lower byte which represents the 8 least significant bits of the 16-bit playback base register. reads from this register return the same value which was written. when set for mode 1 or sdc, this register is used for both the playback and cap- ture base registers. alternate feature enable i (i16) default = 0000eee0 d7 d6 d5 d4 d3 d2 d1 d0 rbc res cmce pmce sf1 sf0 spe dacz dacz dac zero: this bit will force the out- put of the playback channel to ac zero when an underrun error occurs 1 - go to center scale 0 - hold previous valid sample spe dsp serial port enable. when set, audio data from the adcs is sent out sdout and audio data from sdin is sent to the dacs. mce in r0 must be set to change this bit. this bit is initialized through the hardware configuration data. 1 - enable serial port 0 - disable serial port. sf1,sf0 dsp serial format. selects the format of the serial port when en- abled by spe. mce in r0 must be set to change these bits. these bits are initialized through the hardware configuration data. 0 - 64-bit enhanced. figure 6. 1 - 64-bit. figure 7. 2 - 32-bit. figure 8. 3 - adc/dac. figure 9. pmce playback mode change enable. when set, it allows modification of the stereo/mono and audio data for- mat bits (d7-d4) for the playback channel, i8. mce in r0 must be used to change the sample fre- quency. cmce capture mode change enable. when set, it allows modification of the stereo/mono and audio data for- mat bits (d7-d4) for the capture channel, i28. mce in r0 must be used to change the sample fre- quency in i8. alternate feature enable ii (i17) default = 0000x000 d7 d6 d5 d4 d3 d2 d1 d0 test test test test rbc res rbc hpf hpf high pass filter: this bit enables a dc-blocking high-pass filter in the digital filter of the adc. this filter forces the adc offset to 0. 0 - disabled 1 - enabled test factory test. these bits are used for factory testing and must remain at 0 for normal operation. ds252pp2 CS4235 crystalclear low cost isa audio system tm 39 left dac2 volume (i18) default = 00000111 d7 d6 d5 d4 d3 d2 d1 d0 ld2om ld2im rbc ld2a4 ld2a3 ld2a2 ld2a1 ld2a0 note: when aux1r in x18 is set, this register also controls the volume for the laux1 analog input. see i2 description for volume description of laux1. ld2a4-ld2a0 left dac2 attenuation. the least sig- nificant bit represents 1.5 db, with 01000 = 0 db. the total range is +12 db to -33.0 db with 11111 = mut ed. see table 8. ld2im left dac2 input mute. when set, the left dac2 to the input mixer is muted. ld2om left dac2 output mute. when set, the left dac2 to the output mixer is muted. right dac2 volume (i19) default = 00000111 d7 d6 d5 d4 d3 d2 d1 d0 rd2om rd2im rbc rd2a4 rd2a3 rd2a2 rd2a1 rd2a0 note: when aux1r in x18 is set, this register also controls the volume for the raux1 analog input. see i3 description for volume description of raux1. rd2a4-rd2a0 right dac2 attenuation. the least significant bit represents 1.5 db, with 01000 = 0 db. the total range is +12 db to -33.0 db with 11111 = mut ed. see table 8. rd2im right dac2 input mute. when set, the right dac2 to the input mixer is muted. rd2om right dac2 output mute. when set, the right dac2 to the output mixer is muted. control/ram access (i20) default = xxxxxxxx d7 d6 d5 d4 d3 d2 d1 d0 cr7 cr6 cr5 cr4 cr3 cr2 cr1 cr0 this register is identical to ctrlbase+5. for back- wards compatibility, this register is not enabled until pae in x18 is set. when pae is clear, this register is read/writable, but does nothing. cr7-cr0 this register controls the loading of the part?s internal ram as well as in- ternal processor commands. see the hostload procedure section as well as ctrlbase+5 register description for more details. ram access end (i21) default = xxxxxxxx d7 d6 d5 d4 d3 d2 d1 d0 re7 re6 re5 re4 re3 re2 re1 re0 this register is identical to ctrlbase+6. for back- wards compatibility, this register is not enabled until pae in x18 is set. when pae is clear, this register is read/writable, but does nothing. re7-re0 a 0 written to this location resets the previous location, i20, from data download mode, to command mode. alternate sample frequency select (i22) default = 00000000 d7 d6 d5 d4 d3 d2 d1 d0 srediv5div4div3div2div1div0 cs2 cs2 clock 2 base select. this bit selects the base clock frequency used for generating the audio sample rate. note that the part uses only one crystal to generate both clock base frequencies. this bit can be disabled by setting ifse in x11. 0 - 24.576 mhz base 1 - 16.9344 mhz base ds252pp2 CS4235 crystalclear low cost isa audio system tm 40 div5 - div0 clock divider. these bits select the audio sample frequency for both cap- ture and playback. these bits can be overridden by ifse in x11. fs = (2*xt)/(m*n) xt = 24.576 mhz cs2 = 0 xt = 16.9344 mhz cs2 = 1 n = div5-div0 16 n 49 for xt = 24.576 mhz 12 n 33 for xt = 16.9344 mhz (m set by osm1,0 in i10) m = 64 for fs > 24 khz m = 128 for 12 khz < fs 24 khz m = 256 for fs 12 khz sre alternate sample rate enable. when this bit is set to a one, bits 0-3 of i8 will be ignored, and the sample fre- quency is then determined by cs2, div5-div0, and the oversampling mode bits osm1, osm0 in i10. note that this register can be overridden (disabled) by ifse in x11. extended register access (i23) default = 00000xx0 d7 d6 d5 d4 d3 d2 d1 d0 xa3 xa2 xa1 xa0 xrae xa4 res rbc xa4 extended register address bit 4. along with xa3-xa0, enables ac- cess to extended registers x16 through x31. mode 3 only. xrae extended register access enable. setting this bit converts this register from the extended address register to the extended data register. to con- vert back to an address register, r0 must be written. mode 3 only. xa3-xa0 extended register address. along with xa4, sets the register number (x0-x31) accessed when xrae is set. mode 3 only. see the wss ex- tended register section for more details. alternate feature status (i24) default = x0000000 d7 d6 d5 d4 d3 d2 d1 d0 res rbc ci pi cu co po pu pu playback underrun: when set, indicates the dac has run out of data and a sample has been missed. po playback overrun: when set, indicates that the host attempted to write data into a full fifo and the data was discarded. co capture overrun: when set, indicates that the adc had a sample to load into the fifo but the fifo was full. in this case, this bit is set and the new sample is discarded. cu capture underrun: indicates the host has read more data out of the fifo than it contained. in this condition, the bit is set and the last valid byte is read by the host. pi playback interrupt: indicates an interrupt is pending from the play- back dma count registers. ci capture interrupt: indicates an interrupt is pending from the capture dma count registers. the pi and ci bits are reset by writing a "0" to the particular interrupt bit or by writing any value to the status register (r2). ds252pp2 CS4235 crystalclear low cost isa audio system tm 41 compatibility id (i25) default = 00000011 d7 d6 d5 d4 d3 d2 d1 d0 v2 v1 v0 cid4 cid3 cid2 cid1 cid0 cid4-cid0 chip identification. distinguishes between this chip and previous codec chips that support this register set. this register is fixed to indicate code compatibility with the cs4236. x25 or c1 should be used to further differentiate between parts that are compatible with the cs4236. all chips: 00011 - cs4236, cs423xb, CS4235 00010 - cs4232/cs4232a 00000 - cs4231/cs4231a v2-v0 version number. as enhancements are made to the part, the version number is changed so software can distinguish between the different ver- sions. 000 - compatible with the cs4236 these bits are fixed for compatibility with the cs4236. register x25 or c1 may be used to differentiate be- tween the cs4236 and newer chips. mono input control (i26) default = exxxeeee d7 d6 d5 d4 d3 d2 d1 d0 mim rbc rbc res mia3 mia2 mia1 mia0 mia3-mia0 mono input attenuation. when mim is 0, these bits set the level of min summed into the mixer. these bits are initialized through the hardware configuration data, serial port con- trol byte. 0000 = 0 db. 0001-1111 = -9 db mim mono input mute. in mode 3, mim mutes the min analog input to the left output mixer channel. mimr in x4 mutes min analog input to the right output mixer channel. in mode 2, mim mutes both left and right channels. the mono input pro- vides mix for the "beeper" function in most personal computers. this bit is initialized through the hardware con- figuration data, serial port control byte. 0 - no mute 1 - muted left master output volume (i27) default = 00100011 d7 d6 d5 d4 d3 d2 d1 d0 lom los1 los0 log4 log3 log2 log1 log0 when hardware volume is enabled, vcen in c8 or x24 is set, this register will change based on external buttons. log4-log0 left output, lout, master gain. log0 is the least significant bit and represents -2 db, with 00011 = 0 db. the span is nominally +6 db to -56 db. see table 9. los1,0 left output mixer select. these bits select and attenuation into the left output master gain stage, log4-0. 00 - -16 db 01 - 0 db 10 - -8 db 11 - -24 db lom left output mute. when set to 1, the left output, lout, is muted. ds252pp2 CS4235 crystalclear low cost isa audio system tm 42 capture data format (i28) default = x0x0xxxx d7 d6 d5 d4 d3 d2 d1 d0 rbc16brbcs/ m res res res res s/ m stereo/mono select: this bit deter- mines how the capture audio data stream is formatted. selecting stereo will result with alternating samples representing left and right audio channels. selecting mono only cap- tures data from the left audio channel. mce (r0) or cmce (i16) must be set to modify s/ m. see changing audio data formats sec- tion for more details. 0 - mono 1 - stereo 16b selects between 8-bit unsigned and 16-bit signed data for capture. the capture data format can be different than the playback data format. mce (r0) or cmce (i16) must be set to modify this register. see changing audio data formats section for more details. 0 - 8-bit unsigned data 1 - 16-bit signed data right master output volume (i29) default = 00100011 d7 d6 d5 d4 d3 d2 d1 d0 rom ros1 ros0 rog4 rog3 rog2 rog1 rog0 when hardware volume is enabled, vcen in c8 or x24 is set, this register will change based on external buttons. rog4-rog0 right output, rout, master gain. rog0 is the least significant bit and represents -2 db, with 00011 = 0 db. the span is nominally +6 db to -56 db. see table 9. ros1,0 right output mixer select. these bits select and attenuation into the right output master gain stage, rog4-0. 00 - -16 db 01 - 0 db 10 - -8 db 11 - -24 db rom right output mute. when set to 1, the right output, rout, is muted. capture upper base (i30) default = 00000000 d7 d6 d5 d4 d3 d2 d1 d0 cub7 cub6 cub5 cub4 cub3 cub2 cub1 cub0 cub7-cub0 capture upper base: this register is the upper byte which represents the 8 most significant bits of the 16-bit capture base register. reads from this this register returns the same value that was written. capture lower base (i31) default = 00000000 d7 d6 d5 d4 d3 d2 d1 d0 clb7 clb6 clb5 clb4 clb3 clb2 clb1 clb0 clb7-clb0 lower base bits: this register is the lower byte which represents the 8 least significant bits of the 16-bit capture base register. reads from this register returns the same value which was written. ds252pp2 CS4235 crystalclear low cost isa audio system tm 43 wss extended registers the windows sound system codec contains three sets of registers: r0-r3, i0-i31, and x0- x31. r0-r3 are directly mapped to the isa bus through wssbase+0 through wssbase+3 re- spectively. r0 and r1 provide access to the indirect registers i0-i31. the third set of registers are extended registers x0-x31 that are indirectly mapped through the wss register i23. i23 acts as both the extended address and extended data register. these extended registers are only avail- able when in mode 3. accessing the x registers requires writing the register address to i23 with xrae set. when xrae is set, i23 changes from an address regis- ter to a data register. subsequent accesses to i23 access the extended data register. to convert i23 back to the extended address register, r0 must be written which internally clears xrae. as- suming the part is in mode 3, the following steps access the x registers: 1. write 17h to r0 (to access i23). r1 is now the extended address register . 2. write the desired x register address to r1 with xrae = 1. r1 is now the extended data register . 3. write/read x register data from r1. to read/write a different x register: 4. write 17h to r0 again. (resets xrae) r1 is now the extended address register . 5. write the new x register address to r1 with xrae = 1. r1 is now the new extended data register . 6. read/write new x register data from r1. address reg. register name wssbase+0 r0 reset address wssbase+1 r1 address/data access i23 indexed address/data extended register access (i23) d7 d6 d5 d4 d3 d2 d1 d0 xa3 xa2 xa1 xa0 xrae xa4 res rbc table 11. wss extended register control index register name x0 reserved, backwards compatible x1 reserved, backwards compatible x2 mic volume x3 mic volume (same as x2) x4 synthesis and input mixer control x5 right input mixer control x6 left fm synthesis mute x7 right fm synthesis mute x8 left dsp serial port mute x9 right dsp serial port mute x10 reserved, backwards compatible x11 dac1 mute and ifse enable x12 independent adc sample freq. x13 independent dac sample freq. x14 reserved, backwards compatible x15 reserved, backwards compatible x16 left wavetable serial port mute x17 right wavetable serial port mute x18 3d enable & ram port enable x19 fm volume scaling x20 reserved x21 reserved x22 reserved x23 (c2) 3d space control x24 (c8) wavetable & volume control x25 chip version and id x26 (cb+0) joystick control x27 (cb+1) e 2 prom interface x28 (cb+2) power down control 1 x29 (c9) power down control 2 x30 (cb+7) global status x31 reserved table 12. wss extended registers ds252pp2 CS4235 crystalclear low cost isa audio system tm 44 address d7 d6 d5 d4 d3 d2 d1 d0 wssbase+0 r0 init mce trd ia4 ia3 ia2 ia1 ia0 wssbase+1 r1 id7 id6 id5 id4 id3 id2 id1 id0 i23 xa3 xa2 xa1 xa0 xrae xa4 - - xa4 - xa0d7d6d5d4d3d2d1d0 x0 -------- x1 -------- x2 lmim lmom mbst mg4 mg3 mg2 mg1 mg0 x3 rmim rmom mbst mg4 mg3 mg2 mg1 mg0 x4 mimr lis1 lis0 ifm - - - - x5 - ris1 ris0 - - - - - x6 lfmm------- x7 rfmm------- x8 lspm------- x9 rspm------- x10 -------- x11 ld1imrd1imifse----- x12 srad7 srad6 srad5 srad4 srad3 srad2 srad1 srad0 x13 srda7 srda6 srda5 srda4 srda3 srda2 srda1 srda0 x14 -------- x15 -------- x16 lwm------- x17 rwm------- x18 pae - aux1r 3den dspd1 psh - dlen x19 - fms2 fms1 fms0 - - - - x20 -------- x21 -------- x22 -------- x23 (c2) spc3 spc2 spc1 spc0 - - - - x24 (c8) vcie vcf1 - - wten vcen dmclk bres x25 v2 v1 v0 cid4 cid3 cid2 cid1 cid0 x26 (cb+0) - - consw - - - jr1 jr0 x27 (cb+1) ich - - - - din/een dout clk x28 (cb+2) pdwn src vref mix adc dac proc fm x29 (c9) reset - - - - mixcd dac2 sport x30 (cb+7) cwss ictrl isb iwss impu wdt imv - x31 -------- table 13. extended register bit summary control registers for the extended registers extended registers: (x0-x31) ds252pp2 CS4235 crystalclear low cost isa audio system tm 45 mic aux1 (line in) aux 2 (cdrom) line out atten. x4l x5r 20db gain x2 pnp isa interface mute x2l, x3r * mute i2l, i3r mute i4l, i5r * mute i2l, i3r mute i4l, i5r gain x2 * gain i2l i3r s s s s s s s s s s s s s s s mute x2l, x3r gain i4l i5r s s s s s s loopback enable i0l, i1r s s s s s atten. i6l i7r fm syn. enable x4 s s s s mute x11l x11r mute x8l x9r s mute i6l i7r s s s s s s s dsp port enable i16 cs9236 serial port mute x16l x17r s wavetable enable c8 up/down/mute s * i2/i3 can be remapped to be controlled through i18/i19. analog input mixer adc1 dac1 dac2 s s s s s gain i27l i29r s mute i27l i29r s atten. x27l x29r s s analog output mixer s mute i18l i19r s mute i18l i19r gain i18l i19r s s s s s dspd1 enable x18 loop enable x18 s s s s s mute x6l x7r record playback s cs4610 serial port s atten. i26 s s s mute i26l x4r s s min figure 4. mixer block diagram ds252pp2 CS4235 crystalclear low cost isa audio system tm 46 reserved (x0) default = xxxxxxxx d7 d6 d5 d4 d3 d2 d1 d0 rbc rbc rbc rbc rbc rbc rbc rbc rbc reserved, backwards compatible. reserved (x1) default = xxxxxxxx d7 d6 d5 d4 d3 d2 d1 d0 rbc rbc rbc rbc rbc rbc rbc rbc rbc reserved, backwards compatible. mic volume (x2) default = 01011111 d7 d6 d5 d4 d3 d2 d1 d0 lmim lmom mbst mg4 mg3 mg2 mg1 mg0 mg4-mg0 microphone gain. the least signifi- cant bit represents 1.5 db, where 01111 = 0 db and 11110 = -22.5 db. when all bits are 1, the mic is muted with one exception. if mbst = 1 when going f rom 11110 to 11111, t he mic volume does not change. the attenuation steps are shown in table 9. mbst microphone 20 db boost. when set to 1, the mic signal is gained by 20 db. lmom microphone left output mixer mute. when set to 1, the signal to the left channel output mixer is muted. lmim microphone left input mixer mute. when set to 1, the signal to the left channel input mixer is muted. right channel mic (x3) default = 01011111 d7 d6 d5 d4 d3 d2 d1 d0 rmim rmom mbst mg4 mg3 mg2 mg1 mg0 mg4-mg0 microphone gain. the least significant bit represents 1.5 db, with 01111 = 0 db. these are the same bits as in x2. see table 9. mbst microphone 20 db boost. when set to 1, the mic signal is gained by 20 db. this is the same bit as in x2. rmom microphone right output mixer mute. when set to 1, the signal to the right channel output mixer is muted. rmim microphone right input mixer mute. when set to 1, the signal to the right channel input mixer is muted. synthesis and input mixer control (x4) default = e00exxxx d7 d6 d5 d4 d3 d2 d1 d0 mimr lis1 lis0 ifm rbc rbc res res ifm internal fm enable. when set to 1, the internal fm synthesis engine is enabled. this bit can be set through the hardware configuration data in the eeprom. lis1-lis0 left input mixer summer attenuator. this attenuates the inputs to the left input mixer to enable overload pro- tection when multiple input sources are utilized. 00 - 0 db 01 - -6 db 10 - -12 db 11 - -18 db ds252pp2 CS4235 crystalclear low cost isa audio system tm 47 mimr mono input mute to the right output mixer. when set to 1, the min signal to the right output mixer is muted. the default state of this bit is set by mim in the hardware configuration data, mono & dsp port byte. right input mixer control (x5) default = x00xxxxx d7 d6 d5 d4 d3 d2 d1 d0 rbc ris1 ris0 res res res res res ris1-ris0 right input mixer summer attenuator. this attenuates the inputs to the right input mixer to enable overload protection when multiple input sources are utilized. 00 - 0 db 01 - -6 db 10 - -12 db 11 - -18 db left fm synthesis mute (x6) default = exxxxxxx d7 d6 d5 d4 d3 d2 d1 d0 lfmm res rbc rbc rbc rbc rbc rbc lfmm left fm mute. when set to 1, the left internal fm input to dac2 is muted. the default state of this bit is the inverse of ifm in the hardware configuration data, global configura- tion byte. right fm synthesis mute (x7) default = exxxxxxx d7 d6 d5 d4 d3 d2 d1 d0 rfmm res rbc rbc rbc rbc rbc rbc rfmm right fm mute. when set to 1, the right internal fm input to dac2 is muted. the default state of this bit is the inverse of ifm in the hardware configuration data, global configura- tion byte. left dsp serial port mute (x8) default = exxxxxxx d7 d6 d5 d4 d3 d2 d1 d0 lspm res rbc rbc rbc rbc rbc rbc lspm left dsp serial port mute. when set to 1, the left dsp serial port input (sdin) is muted. the default state of this bit is the inverse of spe in the hardware configuration data, mono & dsp port byte. right dsp serial port mute (x9) default = exxxxxxx d7 d6 d5 d4 d3 d2 d1 d0 rspm res rbc rbc rbc rbc rbc rbc rspm right dsp serial port mute. when set to 1, the right dsp serial port input (sdin) is muted. the default state of this bit is the inverse of spe in the hardware configuration data, mono & dsp port byte. reserved (x10) default = xxxxxxxx d7 d6 d5 d4 d3 d2 d1 d0 rbcresrbcrbcrbcrbcrbcrbc rbc reserved, backwards compatible. dac1 mute and ifse enable (x11) default = 110xxxxx d7 d6 d5 d4 d3 d2 d1 d0 ld1im rd1im ifse res res res res res ifse independent sample freq. enable. when set to 1, the extended registers x12 and x13 are used to set the sample rate, and registers i8, i10 (osm1,0), and i22 are ignored. x12 and x13 cannot be modified un- less this bit is set to 1. rd1im right dac1 input mixer mute. when set to 1, the output from the right dac1 is muted to the right in- put mixer. see figure 4. ds252pp2 CS4235 crystalclear low cost isa audio system tm 48 ld1im left dac1 input mixer mute. when set to 1, the output from the left dac1 is muted to the left input mixer. see figure 4. independent adc fs (x12) default = xxxxxxxx d7 d6 d5 d4 d3 d2 d1 d0 srad7 srad6 srad5 srad4 srad3 srad2 srad1 srad0 srad7-srad0 sample rate frequency select for the a/d converter. see table 10. independent dac fs (x13) default = xxxxxxxx d7 d6 d5 d4 d3 d2 d1 d0 srda7 srda6 srda5 srda4 srda3 srda2 srda1 srda0 srda7-srda0 sample rate frequency select for the d/a converter. see table 10. reserved, backwards compatible (x14) default = xxxxxxxx d7 d6 d5 d4 d3 d2 d1 d0 rbc rbc rbc rbc rbc rbc rbc rbc rbc reserved, backwards compatible. reserved, backwards compatible (x15) default = xxxxxxxx d7 d6 d5 d4 d3 d2 d1 d0 rbc rbc rbc rbc rbc rbc rbc rbc rbc reserved, backwards compatible. left wavetable serial port mute (x16) default = exxxxxx d7 d6 d5 d4 d3 d2 d1 d0 lwm res rbc rbc rbc rbc rbc rbc lwm left wavetable serial port mute. when set, the left wavetable serial input to dac2 is muted. the default state of this bit is the inverse of wten in the hardware configura- tion data, global configuration byte. right wavetable serial port mute (x17) default = e0000000 d7 d6 d5 d4 d3 d2 d1 d0 rwmresrbcrbcrbcrbcrbcrbc rwm right wavetable serial port mute. when set, the right wavetable se- rial input to dac2 is muted. the default state of this bit is the inverse of wten in the hardware configura- tion data, global configuration byte. 3d and ram port enable (x18) default = 0xeeeex0 d7 d6 d5 d4 d3 d2 d1 d0 pae res aux1r 3den dspd1 psh res dlen dlen digital loopback enable. when set, the input to dac1 to comes from the adcs. while dlen is on, no other data is sent to dac1. this provides a test path that is generally not used in normal operation. psh playback sample hold. when set, the last sample is held in dac1 when pen is cleared. when clear, zero is sent to dac1 when pen is cleared. dspd1 dsp port controls dac1. when set, the serial dsp port controls dac1 in- stead of the isa playback fifo. 3den 3d sound enable. when set, 3d sound is enabled on l/rout. this bit is also controlled through c3. aux1r aux1 remap. when set, writes to i18/19 (dac2 volume) also control the aux1 volume. when clear, i18/19 control dac2 volume and i2/3 control aux1 volume. this bit provides some backwards compatibil- ity when aux1 analog inputs are substituted for line analog inputs which are no longer available. pae processor access enable. when set, i20/21 provide access to the proces- sor identically to ctrlbase+5/+6 respectively. ds252pp2 CS4235 crystalclear low cost isa audio system tm 49 fm volume scaling (x19) default = xeeexxxx d7 d6 d5 d4 d3 d2 d1 d0 res fms2 fms1 fms0 res res res res fms2-fms0 fm volume scaling relative to wave- table digital input. these bits are provided for backwards compatibility with previous chips. these bits are initialized through hardware configu- ration data. 010 - 0 db 011 - +6 db 100 - -12 db 101 - -6 db 110 - +12 db 111 - +18 db reserved (x20) default = xxxxxxxx d7 d6 d5 d4 d3 d2 d1 d0 res res res res res res res res res reserved. could read as 0 or 1. reserved (x21) default = xxxxxxxx d7 d6 d5 d4 d3 d2 d1 d0 res res res res res res res res res reserved. could read as 0 or 1. reserved (x22) default = xxxxxxxx d7 d6 d5 d4 d3 d2 d1 d0 res res res res res res res res res reserved. could read as 0 or 1. 3d space control (x23) default = 0000xxxx d7 d6 d5 d4 d3 d2 d1 d0 spc3 spc2 spc1 spc0 res res res res this register and c2 access the same data. spc3-spc0 space control for 3d sound. control?s the "width" of the sound ex- pansion with increasing numbers giving decreasing space affects. the least sigificant bit represents 1.5 db of attenuation, with 0000 = 0 db (full space affect). cs9236 wavetable control (x24) default = 0exxee00 d7 d6 d5 d4 d3 d2 d1 d0 vcie vcf1 res res wten vcen dmclk bres this register and c8 access the same data. bres force breset low. when set, the breset pin is forced low. typically used for power management of pe- ripheral devices. dmclk disable mclk. when set, the mclk pin of the cs9236 wavetable syn- thesizer serial interface is forced low providing a power savings mode. vcen volume control enable. when set, the up, down, and mute pins be- come active and provide hardware master volume control for the line outputs. note that this bit can be in- itialized at power-up through hardware configuration data, misc. configuration byte. wten wavetable serial port enable. when, set, the cs9236 single-chip wave- table music synthesizer serial port pins are enabled. wten can be in- itialized in the e 2 prom hardware configuration data, global configura- tion byte. ds252pp2 CS4235 crystalclear low cost isa audio system tm 50 vcf1 hardware volume control format. this bit controls the format of the up, down, and mute pins. vcf1 is initialized in the e 2 prom hard- ware configuration data, global configuration byte. 0 - mute is a momentary button. pressing mute toggles between mute and un-mute. pressing up or down will always un-mute. 1 - mute is not used. pressing the up and down buttons simultane- ously causes the volume to mute. pressing up or down singularly will un-mute. vcie volume control interrupt enable. when set, the hardware volume control pins cause interrupts, when pressed, on the wssint pin. the status is available in ctrlbase+7, imv bit. the imv bit is cleared by reading ctrlbase+7. chip version and id (x25) default = 11011101 d7 d6 d5 d4 d3 d2 d1 d0 v2 v1 v0 cid4 cid3 cid2 cid1 cid0 cid5-cid0 chip identification. distinguishes between this chip and other codec chips that support this register set. this register is identical to c1 and replaces the id register in i25. 11101 - CS4235 v2-v0 version number. as enhancements are made, the version number is changed so software can distinguish between the different versions of the same chip. 100 - revision a 101 - revision b 110 - revision c joystick control (x26) default = xx0x0x01 d7 d6 d5 d4 d3 d2 d1 d0 rbc rbc consw rbc zero rbc jr1 jr0 x26 and ctrlbase+0 access the same data with the exception that the xtal bit in ctrlbase is replaced with zero in this register. jr1,0 joystick rate control. selects operating speed of the joystick (changes the trigger threshold for the x/y coordi- nates). 00 - slowest speed 01 - medium slow speed 10 - medium fast speed 11 - fastest speed zero this bit must be written to 0. writing this bit to 1 will disable the entire wss register space. consw controls host interrupt generation when a context switch occurs 0 - no interrupt on context switch 1 - control interrupt generated on context switch e 2 prom interface (x27) ctrlbase+1, default = 1xxxx000 d7 d6 d5 d4 d3 d2 d1 d0 ich rbc rbc rbc rbc din/ een dout clk x27 and ctrlbase+1 access the same data. clk this bit is used to generate the clock for the plug and play e 2 prom. een must be set to 1 to make this bit operational. a 1 sets the scl pin high and a 0 sets the scl pin low. dout this bit is used to output serial data to the plug and play e 2 prom. een must be set to 1 to make this bit op- erational. a 0 causes sda to go low. a 1 releases sda (open-drain). ds252pp2 CS4235 crystalclear low cost isa audio system tm 51 din/een when read (din), this bit reflects the sda pin, which should be serial data output from the plug and play e 2 prom. een and dout must be 1 for this bit to function. when written (een), enables the e 2 prom interface: clk and dout onto the scl/sda pins. writing: 0 - e 2 prom interface disabled 1 - e 2 prom interface enabled ich interrupt polarity - cdrom. when set, the cdint pin is an active high sig- nal. when low, cdint is an active low signal. this bits can be initial- ized through the hardware configuration data. block power down (x28) default = 00000000 d7 d6 d5 d4 d3 d2 d1 d0 pdwn src vref mix adc1 dac1 proc fm this register and ctrlbase+2 access the same data. see ctrlbase+2 for a detailed description of each bit. power management (x29) default = 0xxxx000 d7 d6 d5 d4 d3 d2 d1 d0 reset res res res res mixcd dac2 sport this register and c9 access the same data. sport powers down the serial ports. dac2 powers down dac2 including fm and the cs9236 serial interface. mixcd powers down the analog mixer - with the exception of min, aux2, and the line outputs. reset when this bit goes from a 1 to a 0, a software resdrv is initiated caus- ing the entire chip to be reset and placed in its default power-up con- figuration. access to all registers on this chip will be lost, including this one, since the power-up state for pnp is all resources unassigned. global status (x30) ctrlbase+7, default = 1000000x d7 d6 d5 d4 d3 d2 d1 d0 cwss ictrl isb iwss impu wdt imv res x30 and ctrlbase+7 access the same data. imv hardware master volume control interrupt status. a hardware volume control interrupt is pending when set to 1. master volume interrupts are enabled through vcie in c8/x24. this bit can only be cleared through ctrlbase+7, not x30. wdt watch-dog timer. if an error occurs on the isa bus, the processor will be reset and wdt will be set. impu mpu-401 interrupt status. mpu inter- rupt pending when set to 1. iwss windows sound system interrupt status. wss interrupt pending when set to 1. isb sound blaster interrupt status. sound blaster interrupt pending when set to 1. ictrl control logical device 2 interrupt status. a context switch interrupt is pending when set to 1. cwss context - wss. indicates the current context. 0 - sound blaster emulation 1 - windows sound system reserved (x31) default = xxxxxxxx d7 d6 d5 d4 d3 d2 d1 d0 res res res res res res res res res reserved. could read as 0 or 1. ds252pp2 CS4235 crystalclear low cost isa audio system tm 52 sound blaster interface the sound blaster pro compatible interface is the third physical device in logical device 0. since the wss codec and the sound blaster are mutually exclusive, the wss codec interrupt and playback dma channel are shared with the sound blaster interface. mode switching to facilitate switching between different func- tional modes (i.e. sound blaster and windows sound system), logic is included to handle the switch transparently to the host. no special soft- ware is required on the host side to perform the mode switch. sound blaster direct register interface the sound blaster software interface utilizes 10- bit address decoding and is compatible with sound blaster and sound blaster pro interfaces. 10-bit addressing requires that the upper address bits be 0 to decode a valid address, i.e. no alias- ing occurs. this device requires 16 i/o locations located at the pnp address sbbase. the fol- lowing registers, shown in table 14, are provided for sound blaster compatibility. left/right fm registers, sbbase+0 - sbbase+3 these registers are mapped directly to the appro- priate fm synthesizer registers. mixer address register, sbbase+4, write only this register is used to specify the index address for the mixer. this register must be written be- fore any data is accessed from the mixer registers. the mixer indirect register map is shown in table 15. mixer data register, sbbase+5 this register provides read/write access to a par- ticular mixer register depending on the index address specified in the mixer address register. address description type sbbase+0 left fm status port read sbbase+0 left fm register status port write sbbase+1 left fm data port write only sbbase+2 right fm status port read sbbase+2 right fm register status port write sbbase+3 right fm status port write only sbbase+4 mixer register address write only sbbase+5 mixer data port read/write sbbase+6 reset write only sbbase+8 fm status port read only sbbase+8 fm register port write sbbase+9 fm data port write only sbbase+a read data port read only sbbase+c command/write data write sbbase+c write buffer status (bit 7) read sbbase+e data available status (bit 7) read table 14. sound blaster pro compatible i/o interface ds252pp2 CS4235 crystalclear low cost isa audio system tm 53 reset sbbase+6, write only when bit d[0] of this register is set to a one and then set to a zero, a reset of the sound blaster interface will occur. read data port sbbase+a, read only when bit d[7] of the data available register, sbbase+e, is set =1 then valid data is available in this register. the data may be the result of a command that was previously written to the command/write data register or digital audio data. command/write data sbbase+c, write only the command/write data register is used to send sound blaster pro commands. write buffer status, sbbase+c, read only the write buffer status register bit d[7] indi- cates when the sbpro interface is ready to accept another command to the command/write data register. d[7]=1 indicates ready. d[7]=0 in- dicates not ready. sound blaster mixer registers the sound blaster mixer registers are shown in table 15. reset register, mixer index 00h writing any value to this register will reset the mixer to default values. vo i c e vo l u m e r e g i s t e r, mixer index 04h, default = 99h this register provides 8 steps of voice volume control each for the right and left channels. microphone mixing register, mixer index 0ah, default = 01h this register provides 4 steps of microphone vol- ume control. register d7 d6 d5 d4 d3 d2 d1 d0 00h data reset 02h reserved 04h voice volume left voice volume right 06h reserved 08h reserved 0ahxxxxx mic mixing 0ch x x x input select x 0ehxxxxxxvstcx 20h reserved 22h master volume left master volume right 24h reserved 26h fm volume left fm volume right 28h cd volume left cd volume right 2ah reserved 2ch reserved 2eh line volume left line volume right table 15. sbpro compatible mixer interface ds252pp2 CS4235 crystalclear low cost isa audio system tm 54 input control register, mixer index 0ch this register selects the input source to the adc. d2,d1 - 00 - microphone 01 - cd audio 10 - microphone 11 - line in output control register, mixer index 0eh vstc - 0 - mono mode 1 - stereo mode master volume register, mixer index 22h, default = 99h this register provides 8 steps of master volume control each for the right and left channels. fm volume register, mixer index 26h, default = 99h this register provides 8 steps of fm volume control each for the right and left channels. cd volume register, mixer index 28h, default = 01h this register provides 8 steps of cd volume control each for the right and left channels. line-in volume register, mixer index 2eh, default = 01h this register provides 8 steps of line-in volume control each for the right and left channels. game port interface the game port logical device software interface utilizes 10-bit address decoding and is located at pnp address gamebase. 10-bit addressing re- quires that the upper address bits be 0 to decode a valid address, i.e. no aliasing occurs. for back- wards compatibility, the game port consists of 8 i/o locations where the lower 6 alias to the same location, which consists of one read and one write register. plug and play configuration capability will allow the joystick i/o base address, gamebase, to be located anywhere within the host i/o address space. currently most games software assume that the joystick i/o port is located at 200h. a write to the gamebase register triggers four timers. a read from the same register returns four status bits corresponding to the joystick fire buttons and four bits that correspond to the out- put from the four timers. a button value of 0 indicates the button is pressed or active. the button default state is 1. when gamebase is written, the x/y timer bits go high. once gamebase is written, each timer output remains high for a period of time deter- mined by the current joystick position. the number in parenthesis below is the joystick con- nector pin number. gamebase+0 - gamebase+7 d7 d6 d5 d4 d3 d2 d1 d0 jbb2 jbb1 jab2 jab1 jbcy jbcx jacy jacx jacx joystick a, coordinate x (pin 3) jacy joystick a, coordinate y (pin 6) jbcx joystick b, coordinate x (pin 11) jbcy joystick b, coordinate y (pin 13) jab1 joystick a, button 1 (pin 2) jab2 joystick a, button 2 (pin 7) jbb1 joystick b, button 1 (pin 10) jbb2 joystick b, button 2 (pin 14) ds252pp2 CS4235 crystalclear low cost isa audio system tm 55 two bits, jr1 and jr0, are located in the con- trol register space (ctrlbase+0) for defining the speed of the game port interface. four dif- ferent rates are software selectable for use with various joysticks and to support older software timing loops with aliasing (roll-over) problems. the game port hardware interface consists of 8 pins that connect directly to the standard game port connector. buttons must have a 1000 pf ca- pacitor to ground and have internal 20 k w pullups resistors. x/y coordinates must have a 5.6 nf capacitor to ground and a 2.2 k w series resistor to the appropriate joystick connector pin. figure 5 illustrates the schematic to the joystick connector. vdf crystal codec 1 nf 1 9 8 4 5 2 10 7 14 12 15 1 nf 5.6 nf 5.6 nf 2.2 k w 2.2 k w midin midout jab2 jbb2 jacy jbcy jbcx jacx jbb1 jab1 3 11 13 6 1 nf 1 nf 2.2 k w 2.2 k w 5.6 nf 5.6 nf figure 5. joystick logic ds252pp2 CS4235 crystalclear low cost isa audio system tm 56 control interface the control logical device includes registers for controlling various functions of the part that are not included in the other logical device blocks. these functions include game port rate control and programmable power management, as well as extra mixing functions. control register interface the control logical device software interface oc- cupies 8 i/o locations, utilizes 12-bit address decoding, and is located at pnp address ctrlbase. if the upper address bits, sa12- sa15 are used, they must be 0 to decode a valid address. this device can also support an inter- rupt. table 16 lists the eight control registers. joystick control ctrlbase + 0, default = xx0x0x01 d7 d6 d5 d4 d3 d2 d1 d0 rbc rbc consw rbc xtal rbc jr1 jr0 jr1,0 joystick rate control. selects operating speed of the joystick (changes the trigger threshold for the x/y coordi- nates). 00 - slowest speed 01 - medium slow speed 10 - medium fast speed 11 - fastest speed xtal crystal oscillator disable. when set, all functions are disabled except access to this register. all registers retain their values in this power-down mode. consw controls host interrupt generation when a context switch occurs 0 - no interrupt on context switch 1 - control interrupt generated on context switch e 2 prom interface ctrlbase+1, default = 1xxxx000 d7 d6 d5 d4 d3 d2 d1 d0 ich rbc rbc rbc rbc din/ een dout clk clk this bit is used to generate the clock for the plug and play e 2 prom. een must be set to 1 to make this bit operational. a 1 sets the scl pin high and a 0 sets the scl pin low. dout this bit is used to output serial data to the plug and play e 2 prom. een must be set to 1 to make this bit op- erational. a 0 causes sda to go low. a 1 releases sda (open-drain). din/een when read (din), this bit reflects the sda pin, which should be serial data output from the plug and play e 2 prom. een and dout must be 1 for this bit to function. when written (een), enables the e 2 prom interface: clk and dout onto the scl/sda pins. writing: 0 - e 2 prom interface disabled 1 - e 2 prom interface enabled ich interrupt polarity - cdrom. when set, the cdint pin is an active high sig- nal. when low, cdint is an active low signal. this bits can be initial- ized through the hardware configuration data. address register ctrlbase+0 joystick control ctrlbase+1 e 2 prom interface ctrlbase+2 block power down ctrlbase+3 control indirect address reg. ctrlbase+4 control indirect data register ctrlbase+5 control/ram access ctrlbase+6 ram access end ctrlbase+7 global status table 16. control logical device registers ds252pp2 CS4235 crystalclear low cost isa audio system tm 57 block power down ctrlbase+2, default = 00000000 d7 d6 d5 d4 d3 d2 d1 d0 pdwn src vref mix adc1 dac1 proc fm fm internal fm synthesizer powered down when set. proc processor set to idle mode. when set, places the internal processor in an idle state. this effects the pnp inter- face, mpu401, and sbpro devices. any command to any one of these interfaces will cause the processor to go active. dac1 dac1 power down. when set, powers down dac1. playback is disabled. adc1 adc1 power down. when set, powers down the adc1. capture is disabled. mix mixer power down. all analog input and output channels are powered down. all outputs are centered around vref if the vref bit is set. a reset is not required to maintain the calibrated state if the mixer is powered down but the vref bit is not set. vref vref power down. when set, powers down the entire mixer. since powering down vref, powers down the entire analog section, some audi- ble pops can occur. src internal sample-rate converters are powered down. only 44.1 khz sam- ple frequency is allowed when this bit is set. pdwn global power down with data reten- tion. when set, the entire chip is powered down, except reads and writes to this register. when this bit is cleared, a full calibration is initi- ated. all registers retain their values; therefore, normal operation can re- sume after calibration is completed. note: software should mute the dacs and mixers and fm volume when asserting any power-down modes to prevent clicks and pops. control indirect address register ctrlbase+3 d7 d6 d5 d4 d3 d2 d1 d0 res res res res ca3 ca2 ca1 ca0 ca3-ca0 address bits to access the control indirect registers c0-c9 through ctrlbase+4 control indirect data register ctrlbase+4 d7 d6 d5 d4 d3 d2 d1 d0 cd7 cd6 cd5 cd4 cd3 cd2 cd1 cd0 cd7-cd0 control indirect data register. this register provides access to the indi- rect registers c0-c9, where ctrlbase+3 selects the actual reg- ister. see the control indirect register section for more details. control/ram access ctrlbase+5 d7 d6 d5 d4 d3 d2 d1 d0 cr7 cr6 cr5 cr4 cr3 cr2 cr1 cr0 cr7-cr0 this register controls the loading of the part?s internal ram. ram sup- port includes hardware configuration and pnp default resource data, as well as program memory. see the hostload procedure section for more information. commands are followed by address and data information. commands: 0x55 - disable pnp key 0x56 - disable crystal key 0x53 - disable crystal key 2 0x5a - update hardware configura- tion data. 0xaa - download ram. address followed by data. (stopped by writ- ing 0 to ctrlbase+6) ds252pp2 CS4235 crystalclear low cost isa audio system tm 58 ram access end ctrlbase+6 d7 d6 d5 d4 d3 d2 d1 d0 re7 re6 re5 re4 re3 re2 re1 re0 re7-re0 a 0 written to this location resets the previous location, ctrlbase+5, from data download mode to com- mand mode. global status ctrlbase+7, default = 0000000x d7 d6 d5 d4 d3 d2 d1 d0 cwss ictrl isb iwss impu wdt imv res imv hardware master volume control interrupt status. when set, hard- ware volume has changed. imv is cleared by reading this status regis- ter. master volume interrupts are enabled through vcie in c8. wdt watch-dog timer. if an error occurs on the isa bus, the processor will be reset and wdt will be set. impu mpu-401 interrupt status. mpu inter- rupt pending when set to 1. iwss windows sound system interrupt status. wss interrupt pending when set to 1. isb sound blaster interrupt status. sound blaster interrupt pending when set to 1. ictrl control logical device 2 interrupt status. a context switch interrupt is pending when set to 1. cwss context - wss. indicates the current context. 0 - sound blaster emulation 1 - windows sound system control indirect registers the control indirect registers are accessed through ctrlbase+3 and ctrlbase+4. ctrlbase+3 is the address register and ctrlbase+4 is the data register used to access c0 through c9 indirect registers. address register name ctrlbase+3 control indirect address ctrlbase+4 control indirect data table 17. control indirect access registers index register name c0 reserved c1 version / chip id c2 3d space control c3 3d enable c4 reserved c5 reserved c6 reserved c7 reserved c8 wavetable & volume control c9 power management table 18. control indirect registers ds252pp2 CS4235 crystalclear low cost isa audio system tm 59 reserved (c0) default = xxxxxxxx d7 d6 d5 d4 d3 d2 d1 d0 rbc res res res res rbc rbc rbc rbc reserved, backwards compatible. version / chip id (c1) default = 11011101 d7 d6 d5 d4 d3 d2 d1 d0 v2 v1 v0 cid4 cid3 cid2 cid1 cid0 cid4-cid0 chip identification. distinguishes between this chip and other codec chips that support this register set. this register is identical to the wss x25 register. 11101 - CS4235 v2-v0 version number. as enhancements are made, the version number is changed so software can distinguish between the different versions of the same chip. 100 - revision a 101 - revision b 110 - revision c 3d space control (c2) default = 0000xxxx d7 d6 d5 d4 d3 d2 d1 d0 spc3 spc2 spc1 spc0 rbc rbc rbc rbc spc3-spc0 space control for 3d sound. control?s the "width" of the sound ex- pansion with increasing numbers giving decreasing space affects. the least sigificant bit represents 1.5 db of attenuation, with 0000 = 0 db (full space affect). 3d enable (c3) default = xxxexxxx d7 d6 d5 d4 d3 d2 d1 d0 rbc rbc rbc 3den res res res res 3den enable 3d sound. when set, 3d sound expansion is enabled on the analog outputs with the amount of 3d enhancement controlled through c2. reserved (c4) default = xxxxxxxx d7 d6 d5 d4 d3 d2 d1 d0 rbc rbc rbc rbc res res res res rbc reserved, backwards compatible. reserved (c5) default = xxxxxxxx d7 d6 d5 d4 d3 d2 d1 d0 rbc rbc rbc rbc rbc rbc rbc rbc rbc reserved, backwards compatible. reserved (c6) default = xxxxxxxx d7 d6 d5 d4 d3 d2 d1 d0 rbc rbc rbc rbc rbc rbc rbc rbc rbc reserved, backwards compatible. reserved (c7) default = xxxxxxxx d7 d6 d5 d4 d3 d2 d1 d0 res res res res res res res res res reserved. must write 0. could read as 0 or 1. ds252pp2 CS4235 crystalclear low cost isa audio system tm 60 wavetable & volume control (c8) default = 0exxee00 d7 d6 d5 d4 d3 d2 d1 d0 vcie vcf1 res res wten vcen dmclk bres bres force breset low. when set, the breset pin is forced low. typically used for power management of pe- ripheral devices. dmclk disable mclk. when set, the mclk pin of the cs9236 wavetable syn- thesizer serial interface is forced low providing a power savings mode. vcen volume control enable. when set, the up, down, and mute pins be- come active and provide hardware master volume control for the line outputs. note that this bit can be in- itialized at power-up through hardware configuration data, misc. configuration byte. wten wavetable serial port enable. when, set, the cs9236 single-chip wave- table music synthesizer serial port pins are enabled. wten can be in- itialized in the e 2 prom hardware configuration data, global configura- tion byte. vcf1 hardware volume control format. this bit controls the format of the up, down, and mute pins. vcf1 is initialized in the e 2 prom hard- ware configuration data, global configuration byte. 0 - mute is a momentary button. pressing mute toggles between mute and un-mute. pressing up or down will always un-mute. 1 - mute is not used. pressing the up and down buttons simultane- ously causes the volume to mute. pressing up or down singularly will un-mute. vcie volume control interrupt enable. when set, the hardware volume control pins cause interrupts, when pressed, on the wssint pin. the status is available in ctrlbase+7, imv bit. power management (c9) default = 0xxxx000 d7 d6 d5 d4 d3 d2 d1 d0 reset res res res res mixcd dac2 sport sport powers down the serial ports. dac2 powers down dac2 including fm and the cs9236 serial interface. mixcd powers down the analog mixer - with the exception of min, aux2, and the line outputs. reset when this bit goes from a 1 to a 0, a software resdrv is initiated caus- ing the entire chip to be reset and placed in its default power-up con- figuration. access to all registers on this chip will be lost, including this one, since the power-up state for pnp is all resources unassigned. ds252pp2 CS4235 crystalclear low cost isa audio system tm 61 mpu-401 interface the mpu-401 is an intelligent midi interface that was introduced by roland in 1984. voyetra technologies subsequently introduced an ibm- pc plug in card that incorporated the mpu-401 functionality. the mpu-401 has become the de- facto standard for controlling midi devices via ibm-pc compatible personal computers. although the mpu-401 does have some intelli- gence, a non-intelligent mode is available in which the mpu-401 operates as a basic uart. by incorporating hardware to emulate the mpu- 401 in uart mode, midi capability is supported. mpu-401 register interface the mpu-401 logical device software interface occupies 2 i/o locations, utilizes 10-bit address decoding, and is located at pnp address mpubase. 10-bit addressing requires that the upper address bits be 0 to decode a valid ad- dress, i.e. no aliasing occurs. the standard base address is 330h. this device also uses an inter- rupt, typically 9. mpubase+0 is the midi transmit/receive port and mpubase+1 is the command/status port. in addition to i/o decodes the only additional func- tionality required from an isa bus viewpoint is the generation of a hardware interrupt whenever data has been received into the receive buffer. midi transmit/receive port, mpubase+0 d7 d6 d5 d4 d3 d2 d1 d0 tr7 tr6 tr5 tr4 tr3 tr2 tr1 tr0 tr7-tr0 the midi transmit/receive port is used to send and receive midi data as well as status information that was returned from a previously sent command. all midi transmit data is transferred through a 16-byte fifo and receive data through a 16-byte fifo. the fifo gives the isa interface time to respond to the asynchronous midi transfer rate of 31.25 k baud. the command/status registers occupy the same address and are used to send instructions to and receive status information from the mpu-401. command register, write only mpubase+1 d7 d6 d5 d4 d3 d2 d1 d0 cs7 cs6 cs5 cs4 cs3 cs2 cs1 cs0 cs7-cs0 for each write to the command/ status register, an appropriate acknowledge is generated. status register, read only mpubase+1 d7 d6 d5 d4 d3 d2 d1 d0 rxs txs cs5 cs4 cs3 cs2 cs1 cs0 cs5-cs1 d0-d5 are the 6 lsbs of the last command written to this port. txs transmit buffer status flag. 0 - transmit buffer not full 1 - transmit buffer full rxs receive buffer status flag 0 - data in receive buffer 1 - receive buffer empty when in "uart" mode, data is received into the receive buffer fifo and a hardware interrupt is generated. data can be received from two sources: midi data via the uart serial input or acknowledge data that is the result of a write to the command register (mpubase+1). the inter- rupt is cleared by a read of the midi receive port (mpubase+0). ds252pp2 CS4235 crystalclear low cost isa audio system tm 62 midi uart the uart is used to convert parallel data to the serial data required by midi. the serial data rate is fixed at 31.25 k baud ( 1%). the serial data format is rs-232 like: 1 start bit, 8 data bits, and 1 stop bit. in multimedia systems, the midi pins are typi- cally connected to the joystick connector as illustrated in figure 5. mpu-401 "uart" mode operation after power-up reset, the interface is in "non- uart" mode. non-uart mode operation is defined as follows: 1. all writes to the transmit port, mpubase+0, are ignored. 2. all reads of the receive port, mpubase+0, return the last received buffer data. 3. all writes to the command port, mpubase+1, are monitored and acknowledged as follows: a. a write of 3fh sets the interface into uart operating mode. an acknowledge is generated by putting an feh into the receive buffer fifo which generates an interrupt. b. a write of a0-a7, abh, ach, adh, afh places an feh into the receive buffer fifo (which generates an interrupt) fol- lowed by a one byte write to the receive buffer fifo of 00h for a0-a7, and abh commands, 15h for ach, 01h for adh, and 64h for afh commands. c. all other writes to the command port are ignored and an acknowledge is gener- ated by putting an feh into the receive buffer fifo which generates an interrupt. uart mode operation is defined as follows: 1. all writes to the transmit port, mpubase+0, are placed in the transmit buffer fifo. whenever the transmit buffer fifo is not empty, the next byte is read from the buffer and sent out the midout pin. the status register, mpubase+1, bit 6, txs is updated to reflect the transmit buffer fifo status. 2. all reads of the receive port, mpubase+0, return the next byte in the receive buffer fifo. when serial data is received from the midin pin, it is placed in the next receive buffer fifo location. if the buffer is full, the last location is overwritten with the new data. the status register, mpubase+1, bit 7, rxs is updated to reflect the new re- ceive buffer fifo state. 3. a write to the command register, mpubase+1, of ffh will return the interface to non-uart mode. 4. all other writes to the command register, mpubase+1, are ignored. fm synthesizer a games-compatible internal fm synthesizer is included which responds to both the sbpro fm synthesis addresses as well as the synbase ad- dresses. to enable the internal fm synthesis engine, the ifm bit in the hardware configuration data, byte 8 (global configuration byte) must be set. this bit is also available in wss register x4. volume control for the internal fm synthesizer is supported through i18 and i19 in the wss ex- tended register space. the synthesizer interface is compatible with the adlib and sound blaster standards. the typical adlib i/o address is synbase = 388h. ds252pp2 CS4235 crystalclear low cost isa audio system tm 63 standard synthesizer i/o map address name type synbase+0 fm status read only synbase+0 fm address 0 write only synbase+1 fm data 0 read/write synbase+2 fm address 1 write only synbase+3 fm data 1 read/write cdrom interface an ide cdrom controller interface is provided that supports enhanced as well as legacy ide cdrom drives. this interface includes two pro- grammable chip selects and on-chip hardware to map dma and interrupt signals to the isa bus. use of the cdrom interface requires an exter- nal 1k e 2 prom to support cdrom plug-and-play, hardware configuration, and firmware patch data. there are five pins that make up the cdrom interface which consist of: cdcs - chip select, combase address cdint - interrupt, comint cdrq - dma request, comdma cdack - dma acknowledge, comdma acdcs - alternate chip select, acdbase the four basic cdrom interface pins are multi- function pins that default to the upper address bits sa12 - sa15. to use the pins as a cdrom interface, a 10 k w pulldown resistor must be placed on mclk. the fifth cdrom pin acdcs is multiplexed with xctl1/ sint/ down. this chip select sup- ports the alternate cdrom chip select used for status. the volume control pin down has the highest precedence; therefore, the vcen bit must be zero to use this pin for the cdrom in- terface. given that vcen is zero, a 10 k w pulldown resistor on sdout converts this pin to acdcs. the range of addresses that acdcs will respond to is programmable via the hard- ware configuration data, byte 5, from one to eight bytes (default = 1 byte). to make the cdrom interface more flexible, one global bit, located in the hardware configu- ration data section - byte 7, allow control over the polarity of the cdrom interrupt pin cdint. ihc defaults to 1 indicating that cdint is an active high interrupt. ihc is also control- lable through ctrlbase+1. cs4610 dsp serial data port the wss codec includes a cs4610 dsp serial audio interface for transferring digital audio data between the part and the cs4610 dc 97 audio accelerator serial device. when spe is set (mce must be 1 to change spe), the serial port pins are enabled; otherwise, they are high-im- pedance pins. the dsp audio serial port is software enabled via the spe bit in the wss codec indirect regis- ter i16 or from the hardware configuration data in the eeprom. the isa interface is fully ac- tive in this mode. the serial port data format is always twos complement 16-bit linear. fsync and sclk are always output from the part when the serial port is enabled. the serial port can be configured in one of four serial port formats, shown in figures 6-9. sf1 and sf0 in i16 select the particular format. mce in r0 must be set to change sf1/0. both left and right audio words are always 16 bit twos complement. when the mono audio format is selected, the right channel output is set to zero and the left channel input is sent to both dac channels. the first format - spf0, shown in figure 6, is called 64-bit enhanced. this format has 64 sclks per frame with a one bit period wide fsync that precedes the frame. the first 16 bits occupy the left word and the second 16 bits oc- ds252pp2 CS4235 crystalclear low cost isa audio system tm 64 fsync sclk sdout 15 14 13 12 ... 16 bits left data 0 15 14 ... 0 16 bits right data 8 zeros sdin 15 14 13 12 ... 16 bits left data 0 15 14 ... 0 16 bits right data int = interrupt bit cen = capture enable pen = playback enable ovr = left overrange or right overrange int 7 zeros cen pen ovr 13 zeros 32 bits ... figure 6. 64-bit enhanced mode (sf1,0 = 00) fsync left data sclk sdout/ 15 14 13 0 ... 15 14 13 0 ... 15 right data 16 clocks 16 clocks 16 clocks 16 clocks sdin ... ... figure 7. 64-bit mode (sf1,0 = 01) sclk fsync left data sdout/ 15 14 13 0 ... 16 clocks 15 14 13 0 ... 16 clocks 15 right data 32 no-clock bit periods ... left data 14 ... ... sdin figure 8. 32-bit mode (sf1,0 = 10) ds252pp2 CS4235 crystalclear low cost isa audio system tm 65 cupy the right word. the last 32 bits contain four status bits and 28 zeros. this is the only mode that contains status information. the second serial format - spf1, shown in fig- ure 7, is called 64-bit mode. this format has 64 sclks per frame, with fsync high transitions at the start of the left data word and low transi- tions at the start of the right data word. both the left and right data words are followed by 16 ze- ros. the third serial format - spf2, shown in fig- ure 8, is called 32-bit mode. this format has 32 sclks per frame and fsync is high for the left channel and low for the right channel. the absolute time is similar to the other two modes but sclk is stopped after the right channel is finished. sclk is held stopped until the start of the next frame (stopped for 32 bit period times). this mode is useful for dsps that do not want the interrupt overhead of the 32 unused bit peri- ods. as an example, if a dsp serial word length is 16 bits, then four interrupts will occur in spf0 and spf1 modes. in mode spf2 the dsp will only be interrupted twice. the fourth serial format - spf3, shown in fig- ure 9, is called adc/dac mode. this format has 64 sclks per frame, with fsync high transitions at the start of the left adc data word and low transitions at the start of the right adc data word. for serial data in, sdin, both the left and right 16-bit dac data word should be fol- lowed by zeros. for serial data out, sdout, both the left and right adc data words are fol- lowed by 16 bits of the dac data words. the dac data words are tapped off the data stream right before the data enters the codec dacs. having the adc and dac data on the sdout allows external modem dsps to cancel the local audio source from the local microphone signal. cs9236 wavetable serial port a digital interface to the cirrus cs9236 single- chip wavetable music synthesizer is provided that allows the cs9236 pcm audio data to be summed digitally into the output digital mixer. this serial port is enabled via the wten bit lo- cated in control register c8/x24 or in the global configuration byte in the hardware configura- tion data. the hardware connections to the cs9236 are illustrated in figure 10. fsync left data sclk sdout 15 right data adc 16 clocks dac 16 clocks adc 16 clocks dac 16 clocks sdin ... ... 15 14 13 ... 0 15 14 13 ... 0 15 14 13 ... 0 15 14 13 ... 0 15 14 13 ... 0 15 14 13 ... 0 dac 16 clocks dac 16 clocks 15 figure 9. adc/dac mode (sf1,0 = 11) ds252pp2 CS4235 crystalclear low cost isa audio system tm 66 the cs9236 data is sent to dac2 which can be summed into the input or output mixer. volume control for the serial port is supported through i18 and i19 in the wss register space. wss codec software description the wss codec must be in mode change en- able mode (mce=1) before any changes to the interface configuration register (i9) or the sam- ple frequency (lower four bits) in the fs & playback data format registers (i8) are allowed. the actual audio data formats, which are the up- per four bits of i8 for playback and i28 for capture, can be changed by setting mce (r0) or pmce/cmce (i16) high. the exceptions are cen and pen which can be changed "on-the- fly" via programmed i/o writes. all outstanding dma transfers must be completed before new values of cen or pen are recognized. calibration the wss codec has four different calibration modes. the selected calibration occurs whenever the mode change enable (mce, r0) bit goes form 1 to 0. the completion of calibration can be determined by polling the auto-calibrate in-progress bit in the error status and initialization register (aci, i11). this bit will be high while the calibration is in progress and low once completed. transfers enabled during calibration will not begin until the calibration cycle has completed. since the part always operates at 44.1 khz internally, all calibration times are based on 44.1 khz sample periods. the calibration procedure is as follows: 1) place the wss codec in mode change enable using the mce bit of the index ad- dress register (r0). 2) set the cal1,0 bits in the interface configura- tion register (i9). 3) return from mode change enable by reset- ting the mce bit of the index address register (r0). 4) wait until 80h not returned 5) wait until aci (i11) cleared to proceed no calibration (cal1,0 = 00) this is the fastest mode since no calibration is performed. this mode is useful for games which require the sample frequency be changed quickly. this mode is also useful when the codec is operating full-duplex and an adc data format change is desired. this is the only calibration mode that does not affect the dacs (i.e. mute the dacs). the no calibration mode takes zero sample periods. converter calibration (cal1,0 = 01) this calibration mode calibrates the adcs and the dacs, but does not calibrate any of the ana- log mixing channels. this is the second longest calibration mode, taking 321 sample periods at 44.1 khz. because the analog mixer is not cali- breset sdata lrclk mclk cs9236 mclk5i lrclk midi_in sout xtal3i pdn rst midout midin joystick connector midi out midi in 100 w 100k w 100k w figure 10. cs9236 wavetable serial port interface ds252pp2 CS4235 crystalclear low cost isa audio system tm 67 brated in this mode, any signals fed through the mixer will be unaffected. the calibration se- quence is as follows: the dacs are muted the adcs are calibrated the dacs are calibrated the dacs are unmuted dac calibration (cal1,0 = 10) this calibration mode only clears the dacs (playback) interpolation filters leaving the adc unaffected. this is the second fastest calibration mode (no cal. is the fastest) taking 120 sample periods at 44.1 khz to complete. the calibration sequence is as follows: the dacs are muted the dac filters are cleared the dacs are unmuted full calibration (cal1, 0 = 11) this calibration mode calibrates all offsets, adcs, dacs, and analog mixers. full calibra- tion will automatically be initiated on power up or anytime the wss codec exits from a full power down state. this is the longest calibration mode and takes 450 sample periods at 44.1 khz to complete. the calibration sequence is as fol- lows: all outputs are muted (dacs and mixer) the mixer is calibrated the adcs are calibrated the dacs are calibrated all outputs are unmuted changing sampling rate the internal states of the wss codec are syn- chronized by the selected sampling frequency. the sample frequency can be set in one of three fashions. the standard wss codec method uses the fs & playback data format register (i8) to set the sample frequency. the changing of either the clock source or the clock frequency divide requires a special sequence for proper wss codec operation: 1) place the wss codec in mode change en- able using the mce bit of the index address register (r0). 2) during a single write cycle, change the clock frequency divide select (cfs) and/or clock 2 base select (c2sl) bits of the fs & playback data format register (i8) to the de- sired value. (the data format may also be changed.) 3) the wss codec resynchronizes its internal states to the new frequency. during this time the wss codec will be unable to respond. writes to the wss codec will not be recog- nized and reads will always return the value 80 hex. 4) the host now polls the wss codecs index address register (r0) until the value 80 hex is no longer returned. on slow processor sys- tems, 80h may go away faster than read from software (the software would never see it). 5) once the wss codec is no longer responding to reads with a value of 80 hex, normal op- eration can resume and the wss codec can be removed from mce. a second method of changing the sample fre- quency is to disable the sample frequency bits in i8 (lower four bits) by setting sre in i22. when this bit is set, osm1 and osm0 in i10, along with the rest of the bits in i22, are used to set the sample frequency. once enabled, these bits can be changed without doing an mce cycle. the third method supports independent sample frequencies (fs) for capture and playback. the independent sample frequency mode is enabled by setting ifse in x11. once enabled, the other two methods for setting fs (i8, i10, and i22) are disabled. the capture (adc) fs is set in x12 and the playback (dac) fs is set in x13. ds252pp2 CS4235 crystalclear low cost isa audio system tm 68 changing audio data formats in mode 1, mce must be used to select the audio data format in i8. since mce causes a calibration cycle, it is not ideal for full-duplex operation. in mode 2 and 3, individual mode change enable bits for capture and playback are provided in register i16. mce (r0) must still be used to select the sample frequency, but pmce (playback) and cmce (capture) allow changing the respective data formats without causing a calibration to occur. setting pmce (i16) clears the playback fifo and allows the upper four bits of i8 to be changed. setting cmce (i16) clears the capture fifo and allows the upper four bits of i28 to be changed. audio data formats the sample frequency is always selected in the fs & playback data format register (i8). in mode 1 the same register, i8, determines the audio data format for both playback and capture; however, in mode 2 and 3, i8 only selects the playback data format and the capture data format is independently selectable in the capture data format register (i28). the wss codec always orders the left channel data before the right channel. note that these definitions apply regardless of the specific for- mat of the data. for example, the left sample always comes first in the data stream regardless of whether the sample is 16-bit or 8-bit in size. there are two data formats supported by the wss codec: 16-bit signed (little endian) and 8- bit unsigned. see figures 12-15. 16-bit signed the 16-bit signed data format is "little endian". this format defines the byte ordering of a multi- byte word as having the least significant byte occupying the lowest memory address. likewise, the most significant byte of a little endian word occupies the highest memory address. the 16-bit signed format (also called 16-bit 2s complement) is the standard method of repre- senting 16-bit digital audio. this format gives 96 db theoretical dynamic range and is the standard for compact disk audio players. this format uses the value -32768 (8000h) to repre- sent maximum negative analog amplitude, 0 for center scale, and 32767 (7fffh) to represent maximum positive analog amplitude. 8-bit unsigned the 8-bit unsigned format is commonly used in the personal computer industry. this format de- livers a theoretical dynamic range of 48 db. this format uses the value 0 (00h) to represent maxi- mum negative analog amplitude, 128 for center scale, and 255 (ffh) to represent maximum positive analog amplitude. the 16-bit signed and 8-bit unsigned transfer functions are shown in figure 11. dma registers the dma registers allow easy integration of this part into isa systems. peculiarities of the isa dma controller require an external count mechanism to notify the host cpu of a full dma buffer via interrupt. the programmable dma base registers provide this service. figure 11. linear transfer functions ds252pp2 CS4235 crystalclear low cost isa audio system tm 69 sample 6 sample 5 sample 4 sample 3 sample 2 sample 1 mono mono mono 32-bit word time 0 7 8 15 16 23 24 31 mono figure 12. 8-bit mono, unsigned audio data sample 3 sample 3 sample 2 sample 2 sample 1 sample 1 left right left 32-bit word time 0 7 8 15 16 23 24 31 right figure 13. 8-bit stereo, unsigned audio data sample 6 sample 5 sample 4 sample 3 sample 2 sample 1 mono mono 32-bit word time 0 15 16 31 23 24 7 8 figure 14. 16-bit mono, signed little endian audio data sample 3 sample 3 sample 2 sample 2 sample 1 sample 1 left right 32-bit word time 0 15 16 31 23 24 7 8 figure 15. 16-bit stereo, signed little endian audio data ds252pp2 CS4235 crystalclear low cost isa audio system tm 70 the act of writing a value to the upper base register causes both base registers to load the current count register. dma transfers are en- abled by setting the pen/cen bit while ppio/cpio is clear. (ppio/cpio can only be changed while the mce bit is set.) once trans- fers are enabled, each sample that is transferred by a dma cycle will decrement the current count register until zero is reached. the next sample after zero generates an interrupt and re- loads the current count registers with the values in the base registers. for all data formats the dma base registers must be loaded with the number of samples, mi- nus one, to be transferred between "dma interrupts". a sample is one to four bytes wide and is defined as all data taken at one instant in time. stereo and mono data contain the same number of samples, and 8-bit data and 16-bit data contain the same number of samples. symbolically: dma base register 16 = n s - 1 where n s is the number of samples transferred between interrupts and the "dma base regis- ter 16 " consists of the concatenation of the upper and lower dma base registers. playback dma registers the playback dma registers (i14/15) are used for sending playback data to the dacs in mode 2 and 3. in mode 1, these registers (i14/15) are used for both playback and capture; therefore, full-duplex dma operation is not pos- sible. when the playback current count register rolls under, the playback interrupt bit, pi, (i24) is set causing the int bit (r2) to be set. the interrupt is cleared by a write of any value to the status register (r2), or writing a "0" to the playback interrupt bit, pi (i24). capture dma registers the capture dma base registers (i30/31) pro- vide a second pair of base registers that allow full-duplex dma operation. with full-duplex op- eration capture and playback can occur simultaneously. these registers are provided in mode 2 and 3 only. when the capture current count register rolls under, the capture interrupt bit, ci, (i24) is set causing the int bit (r2) to be set. the interrupt is cleared by a write of any value to the status register (r2), or writing a "0" to the capture in- terrupt bit, ci (i24). wss codec interrupt the int bit of the status register (r2) always reflects the status of the wss codecs internal interrupt state. a roll-over from any current count register (dma playback, dma capture, or timer) sets the int bit. this bit remains set until cleared by a write of any value to status regis- ter (r2), or by clearing the appropriate bit or bits (pi, ci) in the alternate feature status register (i24). the interrupt enable (ien) bit in the pin control register (i10) determines whether the interrupt assigned to the wss codec responds to the in- terrupt event. when the ien bit is low, the interrupt is masked and the irq pin assigned to the wss codec is held low. however, the int bit in the status register (r2) always responds to the counter. error conditions data overrun or underrun could occur if data is not supplied to or read from the wss codec in an appropriate amount of time. the amount of time for such data transfers depends on the fre- quency selected within the wss codec. should an overrun condition occur during data capture, the last whole sample (before the over- ds252pp2 CS4235 crystalclear low cost isa audio system tm 71 run condition) will be read by the dma inter- face. a sample will not be overwritten while the dma interface is in the process of transferring the sample. should an underrun condition occur in a play- back case the last valid sample will be output (assuming dacz = 0) to the digital mixer. this will mask short duration error conditions. when the next complete sample arrives from the host computer the data stream will resume on the next sample clock. the overrun and underrun error bits in the alter- nate feature status register, i24, are cleared by first clearing the condition that caused the over- run or underrun error, followed by writing the particular bit to a zero. as an example, to clear the playback underrun bit pu, first a sample must be sent to the wss codec, and then the pu bit must be written to a zero. digital hardware description the best example of hardware connection for the different sections of this part is the reference design data sheet. the reference design data sheet contains all the schematics, layout plots and a bill of materials; thereby providing a com- plete example. bus interface the isa bus interface is capable of driving a 24ma data bus load and therefore does not re- quire any external data bus buffering. see the reference design data sheet for a typical con- nection diagram. volume control interface three hardware master volume control pins are supported: volume up, volume down, and mute. hardware volume control is enabled by setting the vcen bit in the hardware configuration data, byte 7 (misc. config. byte). once vcen is set, the xtal1/ acdcs/ down pin converts to the volume down function. the volume con- trol pins affect the master volume control output after the analog output mixer. the up and down pins, when low, increment and decre- ment the master volume. these two pins would use spst momentary switches. the mute pin can either be momentary or non-existent where pressing up and down simultaneously mutes the output volume. the circuit in figure 16, contains optional resistors for emi and esd protection; however, the capacitors are required for switch debounce. pressing the up button, increments the volume. pressing the down button, decrements the vol- ume. holding either of these buttons in the low state causes the volume to to continue changing. the formats are selected by the vcf1 bit, hard- ware configuration data, global config. byte. when vcf1 = 0, the mute function is a momen- tary switch (similar to up and down). when mute goes low the master out volume mutes if it was un-muted and vise-versa (the mute button alternates between mute and un-mute). if the master volume is muted and up or down is pressed, the volume automatically un-mutes. when vcf1 = 1, the mute pin is not used. this is a two-button format where pressing up and down simultaneously mutes the master vol- ume. if the master volume is muted and up or down is individually pressed, the volume auto- matically un-mutes. 10 nf up down mute up gnd mut e down 100 w 10 nf 10 nf 100 w 100 w figure 16. volume control circuit ds252pp2 CS4235 crystalclear low cost isa audio system tm 72 the two formats listed above as illustrated in figure 17. crystal / clock two pins have been allocated to allow the inter- facing of a crystal oscillator: xtali and xtalo. the crystal should be designed as fun- damental mode, parallel resonant, with a load capacitor of between 10 and 20 pf. the capaci- tors connected to each of the crystal pins should be twice the load capacitance specified to the crystal manufacturer. an external cmos clock may be connected to the crystal input xtali in lieu of the crystal. when using an external cmos clock, the xtalo pin must be left floating with no trace or external connection of any kind. general purpose output pins two general purpose outputs are provided to en- able control of external circuitry (i.e. mute function). xctl1 and xctl0 in the wss codec register i10 are output directly to the ap- propriate pin when enabled. pin xctl1/ acdcs/ down is initially control- led by the vcen bit in the hardware configuration data. if vcen is zero, this pin be- comes xctl1 if the sdout pin is sampled high during a high-to-low transition of resdrv. this pin can also output acdcs if the sdout pin is sampled low during a high-to-low transi- tion of the resdrv pin. sdout has an internal pullup resistor. vcen has the highest prece- dence and will cause this pin to convert to the down function whenever vcen is set. reset and power down a resdrv pin places the part into maximum power conservation mode. when resdrv goes high, the pnp registers are reset - all logical de- vices are disabled, all analog outputs are muted, and the voltage reference then slowly decays to ground. when resdrv is brought low, an in- itialization procedure begins which causes a full calibration cycle to occur. when initialization is completed, the registers will contain their reset value and the part will be isolated from the bus. resdrv is required whenever the part is pow- ered up. the initialization time varies based on whether an e 2 prom is present or not and the size of the data in the e 2 prom. after resdrv goes low, the part should not be written to for approximately 200 ms to guarantee that the part is ready to respond to commands. the exact tim- ing is specified in the timing section in the front of this data sheet. software low-power states are available through bits in the control or wss logical device regis- ter space. see the control interface section for more information. address port configuration the part provides a method for motherboards to hide the part from standard pnp (or traditional crystal key) software. bioses can use this method to set the part at a unique address, and report the device as a system dev. node to the operating system. on the high to low transition of the resdrv pin, the part samples the state of the apsel and scl, which have internal 100 k w pullups to +5 v. apsel selects the address port used to configure the part. when apsel is left high, the address port is 0x279 and backwards compat- ible to previous chips and standard pnp software. up gnd mut e down vcf1 = 0 up gnd mute down vcf1 = 1 figure 17. volume control formats ds252pp2 CS4235 crystalclear low cost isa audio system tm 73 when apsel is externally tied to sgnd, the address port is moved to one of two locations, selected by a strapping option on the scl pin. if scl is sampled high (default), then the address port is moved to 0x308. if scl is strapped low with an external 10 k w resistor to sgnd, the address port is moved to 0x388. if the address port is moved (apsel = 0) then the device is no longer pnp compliant; however, it will still respond to all the standard pnp com- mands using the new address port. in addition, the new address port supports the traditional crystal key or the new crystal key 2. multiplexed pin configuration on the high to low transition of the resdrv pin, the part samples the state of the mclk and sdout which have internal 100 k w pullups to +5 v. the state of mclk at the time resdrv is brought low determines the function of the cdrom interface pins. if mclk is sampled high, then cdcs, cdack, cdint, cdrq are used to input sa12, sa13, sa14, sa15 respec- tively. if mclk is sampled low (external pulldown) then cdcs, cdack, cdint, cdrq become the standard cdrom interface pins. the xctl1/ acdcs/ down pin state is first determined by vcen. if vcen is set this pin is forced to the down volume control pin. if vcen is zero, then a strapping option on sdout determines the pin function. if sdout is high (default) on powerup, the pin is forced to the xctl1 general purpose output that tracks the bit by the same name in i10 in the wss space. if sdout is externally pulled low through a 10 k w resistor, then the pin is forced to the alternate cdrom chip select function, acdcs. analog hardware description the analog hardware consist of an mpc level 3-compatible mixer. this section describes the analog hardware needed to interface with these pins. line-level inputs the analog inputs consist of three stereo analog inputs, and one mono input. as shown in fig- ure 4, the input to the adcs comes from the input mixer that selects any combination of the following: aux1, aux2, mic, dac1, dac2, and the output from the analog output mixer. unused analog inputs should be connected to- gether and then connected through a capacitor to analog ground. the analog input interface is designed to accom- modate two stereo inputs and two mono inputs. three of these sources are mixed to the adc. these inputs are: a mono microphone input (mic), a stereo cd-rom input (aux2), and a stereo auxiliary line-level input (aux1). the mic, aux1, and aux2 inputs have paths after their volume controls, to the output mixer. the output mixer has the additional input of a mono input channel. all audio inputs should be capaci- tively coupled. since some analog inputs can be as large as 2 v rms , the circuit shown in figure 18 can be used to attenuate the analog input to 1 v rms which is the maximum voltage allowed for the line-level inputs. 6.8 k w 6.8 k w 1.0 m f 1.0 m f r l 6.8 k w 6.8 k w figure 18. line inputs ds252pp2 CS4235 crystalclear low cost isa audio system tm 74 the aux2 line-level inputs have an extra pin, cmaux2, which provides a pseudo-differential input for both laux2 and raux2. this pin takes the common-mode noise out of the aux2 inputs when connected to the ground coming from the aux2 analog source. connecting the aux2 pins as shown in figure 19 provides extra noise attenuation coming from the cdrom drive, thereby producing a higher quality signal. since the better the resistors match, the better the common-mode attenuation, one percent resistors are recommended. if cmaux2 is not used, it should be connected through an ac cap to ana- log ground. microphone level input the microphone level input, mic, include a se- lectable -22.5 db to +22.5 db gain stage for interfacing to an external microphone. an addi- tional 20 db gain block is also available. the 20 db gain block can be switched off to provide another mono line-level input. figure 20 illus- trates a single-ended microphone input buffer circuit that will support lower gain mics. the cir- cuit in figure 20 supports dynamic mics and phantom-powered mics that use the ring portion of the jack for power. mono input the mono input, min, is useful for mixing the output of the "beeper" (timer chip), provided in all pcs, with the rest of the audio signals. the min pin can be mixed into the output mixer with at a 0 or -9 db level. also, the mim and mimr bits support muting the input to the left and right channels respectively. figure 21 illus- trates a typical input circuit for the mono in. if min is driven from a cmos gate, the 4.7 k w should be tied to agnd instead of va+. al- though this input is described for a low-quality beeper, the input is of the same high-quality as all other analog inputs and may be used for other purposes. line level outputs the analog output section provides a stereo line- level output. the other output types (headphone and speaker) can be implemented with external circuitry. lout and rout outputs should be capacitively coupled to external circuitry. both lout and rout need 1000 pf npo capacitors between the pin and agnd. 6.8 k w 6.8 k w 1.0 m f 1.0 m f raux2 laux2 6.8 k w 6.8 k w 3.4 k w cmaux2 2.0 m f 3.4 k w (all resistors 1%) figure 19. differential cdrom in 0.1 m f 2.7 nf npo 10 m f + 600 w 4.7 k w 47 k w mc33078 or mc33178 vref mi c 1 m f + 0.33 m f x7r 2 k w 47 k w figure 20. microphone input 2.7 nf 47 k w 4.7 k w 0.1 m f min 1 +5va (low noise) or agnd - if cmos source figure 21. mono input ds252pp2 CS4235 crystalclear low cost isa audio system tm 75 miscellaneous analog signals the vref pin is typically 2.2 v and provides a common mode signal for single-supply external circuits. vref only supports light dc loads and should be buffered if ac loading is needed. for typical use, a 0.1 m f in parallel with a 10 m f ca- pacitor should be connected to vref. grounding and layout figure 22 is a suggested layout for motherboard designs and figure 23 is a suggested layout for add-inn cards. for optimum noise performance, the device should be located across a split ana- log/digital ground plane. the digital ground plane should extend across the isa bus pins as well as the internal digital interface pins. dgnd1 is ground for the data bus and should be electrically connected to the digital ground plane which will minimize the effects of the bus interface due to transient currents during bus switching. sgnd1-4 should also be connected to the digital ground plane to minimize coupling into the analog section. figure 24 shows the rec- ommended positioning of the decoupling capacitors. the capacitors must be on the same layer as, and close to, the part. the vias shown go through to the ground and power plane lay- ers. vias and power supply traces should be as large as possible to minimize the impedance. power supplies the power supply providing analog power should be as clean as possible to minimize cou- pling into the analog section and degrading analog performance. the vd1 is isolated from the rest of the power supply pins and provide digital power for the asynchronous parallel isa bus. the vd1 pin can be connected directly to the system digital power supply. 1 digital ground analog ground crystal part power connector digital ground noise di g i t a l g r o u n d n o ise d i g i t a l g r o u n d n o i s e figure 22. suggested motherboard layout ds252pp2 CS4235 crystalclear low cost isa audio system tm 76 cd-rom speaker in speaker out crystal part digital ground analog ground 1 figure 23. suggested add-in card layout pin 1 pin 17 vdf1 pin 66 sgnd2 pin 71 test pin 45 vd1 pin 81 va + pin 18 sgnd1 pin 53 sgnd4 pin 65 vdf2 pin 46 dgnd1 pin 80 agnd pin 79 refflt analog digital pin 98 vdf3 pin 97 sgnd3 1 m f .1 m f .1 m f .1 m f .1 m f .1 m f .1 m f = vias through to power/ground plane figure 24. recommended decoupling capacitor positions ds252pp2 CS4235 crystalclear low cost isa audio system tm 77 vdf1 through vdf3 provide power to internal digital sections of the codec and should be qui- eter than vd1. this can be achieved by using a ferrite bead to the vd1 supply. va provides power to the sensitive analog sec- tions of the chip and should have a clean, regulated supply to minimize power supply cou- pled noise in the analog inputs and outputs. adc/dac filter response plots figures 25 through 30 show the overall fre- quency response, passband ripple, and transition band for the adcs and dacs. figure 31 shows the dacs deviation from linear phase. since the filter response scales based on sample frequency selected, all frequency response plots x-axis are shown from 0 to 1, where 1 is equivalent to fs. therefore, for any given sample frequency, mul- tiply the x-axis values by the sample frequency selected to get the actual frequency. 10 0 - 10 - 20 - 30 - 40 - 50 - 60 - 70 - 80 - 90 - 100 0 . 00 . 10 . 20 . 30 . 40 . 50 . 60 . 70 .8 0 . 91 . 0 input frequency ( x fs) magnitude (db) figure 25. adc filter response 0 . 2 0. 1 0 . 0 -0. 1 - 0 . 2 - 0 . 3 - 0 . 4 - 0 . 5 - 0 . 6 - 0 . 7 - 0 . 8 0 . 00 0 . 05 0 . 10 0 . 15 0 . 20 0 . 25 0 . 30 0 .3 50 . 40 0 . 45 0 . 50 input frequency ( x fs) magnitude (db) figure 26. adc passband ripple 0 - 1 0 - 2 0 - 3 0 - 4 0 - 5 0 - 6 0 - 7 0 - 8 0 - 9 0 - 10 0 0 . 40 0 . 45 0 . 50 0 . 55 0 . 60 0 . 65 0 . 70 input frequency ( x fs) magnitude (db) figure 27. adc transition band ds252pp2 CS4235 crystalclear low cost isa audio system tm 78 10 0 - 10 - 20 - 30 - 40 - 50 - 60 - 70 - 80 - 90 - 100 0 . 00 . 10 . 20 . 30 . 4 0. 50 . 60 . 70 . 80 . 91 . 0 input frequency ( x fs) magnitude (db) figure 28. dac filter response 0 . 2 0 . 1 0 . 0 - 0 . 1 - 0 . 2 - 0 . 3 - 0 . 4 - 0 . 5 - 0 . 6 - 0 . 7 - 0 . 8 0 . 00 0 . 05 0 . 10 0 . 15 0 . 2 0 0 . 25 0 .3 00 . 35 0 .4 00 . 45 0 . 50 input frequency ( x fs) magnitude (db) figure 29. dac passband ripple 0 - 10 - 20 - 30 - 40 - 50 - 60 - 70 - 80 - 90 - 100 0 . 40 0 . 45 0 . 50 0 . 55 0 . 60 0 . 65 0 . 70 input frequency ( x fs) magnitude (db) figure 30. dac transition band 2 . 0 1 . 5 1 . 0 0 . 5 0 . 0 - 0 . 5 - 1 . 0 - 1 . 5 - 2 . 0 0 . 00 0 . 05 0 . 10 0 . 1 5 0 . 20 0 . 2 5 0 . 30 0 .3 50 . 40 0 . 45 0 . 50 input frequency ( x fs) d phase (degrees) figure 31. deviation from linear phase ds252pp2 CS4235 crystalclear low cost isa audio system tm 79 76 100 75 50 1 25 100-pin tqfp (top view) 26 51 s a 1 5 * / c d r q x t a l i c m a u x 2 x t a l o m u t e 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 v d f 3 s g n d 3 midin midout dacka (dack0*) dackb (dack1*) dackc (dack3*) drqa (drq0*) drqb (drq1*) drqc (drq3*) (int5*) irqa (int7*) irqb (int9*) irqc (int11*) irqd (int12*) irqe (int15*) irqf i o c h r d y iow a e n s d 1 s d 2 s d 3 d g n d 1 v d 1 s d 4 s d 5 s d 6 s d 7 sa11 s a 1 0 s a 9 s a 8 s a 7 s a 6 s a 5 s a 4 s a 3 s a 2 s a 1 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 jbcx sdata jacx mclk sgnd2 vdf2 jbcy jacy jbb2 jab2 lrclk sclk sda irqg (int10) sgnd4 up xctl0 scl breset xctl1*/acdcs/down 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 jbb1 jab1 s a 1 3 * / c d a c k s a 1 2 * / c d c s test r e s d r v a p s e l m i n l a u x 2 lout f l t i f l t o r o u t r a u x 2 v a a g n d v r e f r e f f l t laux1 m i c raux1 s a 1 4 * / c d i n t 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 77 i o r s d 0 sdin vdf1 sgnd1 fsync sdout sa0 f l t 3 d * defaults - see individual pin descriptions for more details pin descriptions CS4235 CS4235 crystalclear low cost isa audio system tm 80 ds252pp2 isa bus interface pins sa<11:0> - system address bus, inputs these signals are decoded during i/o cycles to determine access to the various functional blocks within the part as defined by the configuration data written during a plug and play configuration sequence. sa<15:12> - upper system address bus, inputs these signals are multi-function pins, shared with the cdrom, that default to the upper address bits sa12 through sa15. these pins are generally used for motherboard designs that want to eliminate address decode aliasing. using these pins as upper address bits forces the part to only accept valid address decodes when a12-a15 = 0. if these pins are not used for address decodes or for cdrom support, they should be tied to sgnd. these pins are forced to the cdrom interface when a 10 k w resistor is placed on pin mclk to sgnd. sd<7:0> - system data bus, bi-directional, 24 ma drive these signals are used to transfer data to and from the part. aen - address enable, input this signal indicates whether the current bus cycle is an i/o cycle or a dma cycle. this signal is low during an i/o cycle and high during a dma cycle. ior - read command strobe, input this active low signal defines a read cycle to the part. the cycle may be a register read or a read from the part?s dma registers. iow - write command strobe, input this active low signal indicates a write cycle to the part. the cycle may be a write to a control register or a dma register. iochrdy - i/o channel ready, open drain output, 8 ma drive this signal is driven low by the part during isa bus cycles in which the part is not able to respond within a minimum cycle time. iochrdy is forced low to extend the current bus cycle. the bus cycle is extended until iochrdy is brought high. drq dack laux2 - left auxiliary #2 input nominally 1 v rms max analog input for the left aux2 channel, centered around vref. a programmable gain block provides volume control and is located in i4. typically used for the left channel cdrom input. raux2 - right auxiliary #2 input nominally 1 v rms max analog input for the right aux2 channel, centered around vref. a programmable gain block provides volume control and is located in i5. typically used for the right channel cdrom input. cmaux2 - common mode auxiliary #2 input common mode ground input for the laux2 and raux2 inputs. typically connected to the cdrom ground input to provide common-mode noise rejection. the impedance on this pin should be one half the impedance on the laux2 and raux2 inputs. min - mono input nominally 1 v rms max analog input, centered around vref, that goes through a programmable gain stage (i26) into both channels of the output mixer. this is a general purpose mono analog input that is normally used to mix the typical "beeper" signal on most computers into the audio system. refflt - reference filter, input voltage reference used internal to the part. a 0.1 m f and a 1 m f capacitor with short fat traces must be connected between this pin and agnd. no other connections should be made to this pin. analog outputs lout - left line level output analog output from the mixer for the left channel. nominally 1 v rms max centered around vref. a 1000 pf npo capacitor must be attached from this pin to agnd. rout - right line level output analog output from the mixer for the right channel. nominally 1 v rms max centered around vref. a 1000 pf npo capacitor must be attached from this pin to agnd. flt3d - 3d filter a 0.01 m f capacitor must be attached from this pin to agnd. flto - filter output a 1000 pf npo capacitor must be attached between this pin and flti. CS4235 crystalclear low cost isa audio system tm ds252pp2 83 flti - filter input a 1000 pf npo capacitor must be attached between this pin and flto. vref - voltage reference, output all analog inputs and outputs are centered around vref which is nominally 2.1 volts. this pin may be used to level shift external circuitry, although any ac loads should be buffered. midi interface midout - midi out transmit data, output, 4 ma drive this output is used to send midi data serially out to a external midi device. normally connected to pin 12 of the joystick connector for use with breakout boxes. midin - midi in receive data, input - internal pullup this input is used to receive serial midi data from an external midi device. this pin should be connected to pin 15 of the joystick connector for use with breakout boxes. external peripheral signals sda - e 2 prom data pin, bi-directional, open drain, 4 ma sink this open-drain pin must have an external pullup (3.3 k w ) and is used in conjunction with scl to access an external serial e 2 prom. when an e 2 prom is used, the sda pin should be connected to the data pin of the e 2 prom device and provides a bi-directional data port. the e 2 prom is used to set the plug and play resource data. scl - e 2 prom serial clock, output, 4 ma drive (address port selection) when e 2 prom access is enabled, via een in ctrlbase+1, then scl is used as a clock output to the e 2 prom. at power-up, this pin is an input (with an internal 100 k w pullup) that selects between two alternate addresses for the address port used to configure the chip. assuming apsel is strapped low, scl high selects 308h as the address port, and when scl is tied low (with a 10 k w resistor to ground), the address port is 388h. xctl0 - external control, output, 4 ma drive this pin is a general purpose output pin controlled by the xctl0 bit in the wss register i10. breset - buffered reset, output, 4 ma drive this active low signal goes low whenever the resdrv pin goes high. this pin is also software controllable through the bres bit in register c8 in the control logical device space. bres provides a software power down and reset control over devices connected to the CS4235 such as the cs9236 single-chip wavetable music synthesizer. CS4235 crystalclear low cost isa audio system tm 84 ds252pp2 joystick interface jacx, jacy - joystick a coordinates, input these pins are the x/y coordinates for joystick a. they should have a 5.6 nf capacitor to ground and a 2.2 k w resistor to the joystick connector pins 3 and 6, respectively. jab1, jab2 - joystick a buttons, input - internal pullups these pins are the switch inputs for joystick a. they should be connected to joystick connector pins 2 and 7, respectively; as well as have a 1 nf capacitor to ground. jbcx, jbcy - joystick b coordinates, input - internal pullups these pins are the x/y coordinates for the second joystick, joystick b. they should have a 5.6 nf capacitor to ground and a 2.2 k w resistor to the joystick connector pins 11 and 13, respectively. jbb1, jbb2 - joystick b buttons, input these pins are the switch inputs for the second joystick, joystick b. they should be connected to joystick connector pins 10 and 14, respectively; as well as have a 1 nf capacitor to ground. cs4610 dsp serial port interface fsync - frame sync, output, 4 ma drive when the serial port is enabled, spe = 1 in i16, this pin is the serial frame sync output. sclk - serial clock, output, 4 ma drive when the serial port is enabled, spe = 1 in i16, this pin is the serial clock output. sdout - serial data output, output, 4 ma drive (alternate cdrom chip select enable) when the serial port is enabled, spe = 1 in i16, this pin is the serial data output. at power-up, this pin is an input (with an internal 100 k w pullup) that, when pulled low with a 10 k w resistor to sgnd, enables the alternate cdrom chip select pin acdcs. loading must be limited to cmos inputs if this pin has the 10 k w resistor attached. sdin - serial data input, input when the serial port is enabled, spe = 1 in i16, this pin is the serial data input. cs9236 wavetable serial port interface a digital interface to the cs9236 single-chip wavetable music synthesizer is provided that allows the cs9236 pcm audio data to be summed on the CS4235 without the need for an external dac. this serial port is enabled via the wten bit which is located in the global configuration byte in the e 2 prom hardware configuration data, or c8. CS4235 crystalclear low cost isa audio system tm ds252pp2 85 sdata - wavetable serial audio data, input this input supplies the serial audio pcm data to be mixed to the stereo dac2 of the CS4235. the data consists of left and right channel 16-bit data delineated by lrclk. this pin should be connected to the sout output pin on the cs9236. this pin should also have a weak pull-down resistor of approx. 100 k w to minimize power-down currents and allow for stuffing options. lrclk - wavetable serial left/right clock, input this input supplies the serial data alignment signal that delineates left from right data. this pin should be connected to the lrclk output pin on the cs9236. this pin should also have a weak pull-down resistor of approx. 100 k w to minimize power-down currents and allow for stuffing options. mclk - wavetable master clock, output (cdrom enable) this output supplies the 16.9344 mhz master clock that controls all the timing on the cs9236. this pin should be connected to the mclk5i input pin on the cs9236. mclk can be disabled in software using the dmclk bit in c8 in the control logical device space. dmclk provides a partial software power-down mode for the cs9236. at power-up, this pin is an input (with an internal 100 k w pullup) that, when pulled low with a 10 k w resistor to sgnd, enables the cdrom interface (over the upper four isa address pins). cdrom interface the four cdrom pins are multi-function and default to isa upper address bits sa12-sa15. to enable the cdrom port, an external 10 k w resistor must be tied between mclk and sgnd. mclk is sampled on the falling edge of resdrv. the alternate cdrom chip select has its own strapping option to enable acdcs. use of the cdrom interface requires a 1 k e 2 prom to support the plug-and-play data as well as firmware patch data. cdcs - cdrom chip select, output, 4 ma drive this output goes low whenever an address is decoded that matches the value programmed into the cdrom base address register. acdcs - alternate cdrom chip select, output, 4 ma drive this pin, xctl1/ acdcs/ down, is multiplexed with two other functions, and defaults to the xctl1 output which is controlled by the xctl1 bit in the wss i10. this pin can also be configured at a second cdrom chip select, acdcs, to support the alternate ide cdrom decode. to force this pin to the cdrom alternate chip select, an external 10 k w resistor must be tied between sdout and sgnd. acdcs output then goes low whenever an address is decoded that matches the value programmed into the cdrom alternate base address register, acdbase. this pin can also be used as the volume up pin down by setting vcen in control register c0 or the hardware configuration data. vcen has the highest precedence over the other pin functions. CS4235 crystalclear low cost isa audio system tm 86 ds252pp2 cdint - cdrom interrupt, input this pin is used to input an interrupt signal from the cdrom interface. the part can be programmed, through the plug-and-play resource data, to output this signal to the appropriate isa bus interrupt line. the polarity if this input can be programmed through ctrlbase+1 register, bit ich, or the hardware configuration data; the default is active high. cdrq - cdrom dma request, input this pin can be used to input the dma request signal from the cdrom interface. the part can be programmed, through the plug-and-play resource data, to output this signal to the appropriate isa bus drq line. cdack- cdrom dma acknowledge, output, 4 ma drive this pin can be used to output the isa bus-generated dma acknowledge signal to the cdrom interface. volume control the volume control pins are enabled by setting vcen in the hardware configuration data, misc. hardware config. byte. the vcf1 bit in the hardware configuration data, global configuration byte, set the format for the volume control pins. typically a 100 w series resistor and a 10 nf capacitor (required) to ground, capacitor on the switch side of the series resistor, would be included on each pin for esd protection and to help with emi emissions. up - volume up, input - internal pullup this pin is enabled when vcen is set. when up is low, the master volume output is incremented. a 10 nf capacitor to ground is required for switch debounce. down - volume down, input - internal pullup the xctl1/ acdcs/ down is a multiplexed pin that can be used as xctl1, the alternate cdrom chip select, or the volume down pin. this pin is switched to the down function when vcen is set. when down is low, the master volume output is decremented. a 10 nf capacitor to ground is required for switch debounce. mute - volume mute, input - internal pullup the mute pin function can be momentary, or non-existent based on the vcf1 bit. the mute function is enabled when vcen is set. a 10 nf capacitor to ground is required for switch debounce. miscellaneous xtali - crystal input this pin will accept either a crystal, with the other pin attached to xtalo, or an external cmos clock. xtal must have a crystal or clock source attached for proper operation. the crystal frequency must be 16.9344 mhz and designed for fundamental mode, parallel resonance operation. CS4235 crystalclear low cost isa audio system tm ds252pp2 87 xtalo - crystal output this pin is used for a crystal placed between this pin and xtali. if an external clock is used on xtali, this pin must be left floating with no traces or components connected to it. apsel - address port select, input this pin has an internal pull-up of approximately 100 k w . leaving this pin in its default condition, places the pnp/crystal key address port at the standard pnp address of 279h (hex). for motherboard applications, apsel can be tied to sgnd, which will change the address port to one of two other addresses, chosen by a strapping option on pin scl. when resdrv goes inactive, pin scl is forced to an input and sampled. when scl is sampled high (default), the address port changes to address 308h. when scl is sampled low, the address port changes to 388h. add-in cards should leave apsel unconnected test - test this pin must be tied to ground for proper operation. power supplies va - analog supply voltage supply to the analog section of the codec. agnd - analog ground ground reference to the analog section of the codec. this pin should be placed on an analog ground pin separate from other chip grounds. vd1 - isa digital supply voltage digital supply for the isa parallel data bus pins. dgnd1 - isa digital ground digital ground reference for the isa parallel data bus pins. these pins are isolated from the other grounds and should be connected to the digital ground section of the board (see figure 24). vdf1, vdf2, vdf3 - digital filtered supply voltage digital supply for the internal digital section of the codec (except for the parallel data bus). these pins should be filtered, using a ferrite bead, from vd1. sgnd1, sgnd2, sgnd3, sgnd4 - internal digital grounds ground reference for the internal digital portion of the codec. optimum layout is achieved by placing sgnd1/2/3/4 on the digital ground plane with the dgnd pin as shown in figure 24. CS4235 crystalclear low cost isa audio system tm 88 ds252pp2 parameter definitions frequency response frequency response is the deviation in signal level verses frequency. the 0 db reference point is 1 khz. the amplitude corner, ac, lists the maximum deviation in amplitude above and below the 1 khz reference point. the listed minimum and maximum frequencies are guaranteed to be within the ac from minimum frequency to maximum frequency inclusive. total dynamic range tdr is the ratio of the rms sum of the lowest obtainable noise floor, in the presence of a signal, divided by the rms full-scale signal level. the lowest obtainable noise floor is defined as the noise floor measured with the attenuation bits for the volume control at full attenuation - without muting. measured over a 20 hz to 20 khz bandwidth with units in db fs a. (db fs is defined as db relative to full-scale. the "a" indicates an a weighting filter was used.) instantaneous dynamic range or dynamic range idr or dr is the ratio of the rms sum of the noise floor, in the presence of a signal, divided by the rms full-scale signal level, available at any instant in time (no change in gain settings between measurements). measured over a 20 hz to 20 khz bandwidth with units in db fs a. (db fs is defined as db relative to full-scale. the "a" indicates an a weighting filter was used.) total harmonic distortion plus noise thd+n is the ratio of the rms sum of all non-fundamental frequency components, divided by the rms full-scale signal level. tested using a -3 db fs input signal. measured over a 20 hz to 20 khz bandwidth with units in db fs a. (db fs is defined as db relative to full-scale. the "a" indicates an a weighting filter was used.) interchannel isolation the ratio of signal level on the tested channel divided by the stimulus channel level. for inputs, the tested input channel is terminated with 50 w . for outputs, the tested channel is fed digital zeros. units in db. interchannel gain mismatch for the adcs, the difference in input voltage to get an equal code on both channels. for the dacs, the difference in output voltages for each channel when both channels are fed the same code. units in db. paths: a-d-pc: analog in, through adc, onto pc bus pc-d-a: pc bus, through dac, to analog out a-a: analog in to analog out (analog output mixer) detailed information on audio testing and paths can be found in personal computer audio quality measurements document by dr. steven harris and clif sanchez, located at the following web address: http://www.cirrus.com/products/papers/meas/meas.html. CS4235 crystalclear low cost isa audio system tm ds252pp2 89 package parameters d d1 e e1 e1 b 100 1 n a a1 b c d d1 e e1 e1 100-pin tqfp - package code 'q' l1 t symbol description lead count overall height stand off lead width lead thickness terminal dimension package body terminal dimension package body lead pitch foot length lead angle min nom max 0.077 100 0.00 0.14 15.70 15.70 0.40 0.30 0.0 12.0 0.20 0.127 16.00 14.0 16.00 14.0 0.50 0.50 1.66 0.26 0.177 16.30 16.30 0.60 0.70 a1 a c l1 t notes: 1) dimensions in millimeters. 2) package body dimensions do not include mold protrusion, which is 0.25 mm. 3) coplanarity is 0.004 in. 4) lead frame material is al-42 or copper, and lead finish is solder plate. 5) pin 1 identification may be either ink dot or dimple. 6) package top dimensions can be smaller than bottom dimensions by 0.20 mm. 7) the "lead width with plating" dimension does not include a total allowable dambar protrusion of 0.08 mm (at maximum material condition). 8) ejector pin marks in molding are present on every package. CS4235 crystalclear low cost isa audio system tm 90 ds252pp2 appendix a: default pnp data ; eeprom validation bytes db 055h, 0bbh ; eeprom validation bytes: CS4235 db 001h ; eeprom data length upper byte db 014h ; lower byte, listed size = 276 ; hardware configuration data db 000h ; acdbase addr. mask length = 1 bytes db 003h ; db 080h ; mcb: ihcd db 080h ; gcb1: ifm db 005h ; code base byte db 020h ; fm scaling 0 db db 004h ; reserved db 008h ; reserved db 010h ; reserved db 080h ; m+dsp: mim db 000h ; db 000h ; gcb2: no bits set ; hardware mapping data db 004h ; cdbase length = 4 db 048h ; reserved db 075h ; irq selection a & b - b= 7, a=5 db 0b9h ; irq selection c & d - d=11, c=9 db 0fch ; irq selection e & f - f=15, e=12 db 010h ; dma selection a & b - b= 1, a=0 db 003h ; dma c,irq g select. - g= 0, c=3 ; pnp resource header - pnp id for cs4236 ic, oem id = 42 db 00eh, 063h, 042h, 036h, 0ffh,0ffh,0ffh,0ffh,0a9h ; csc4236 ffffffff db 00ah, 010h, 005h ; pnp version 1.0, vendor version 0.5 db 082h, 00eh, 000h, crystal codec, 000h ; ansi id ; logical device 0 (windows sound system & sbpro) db 015h, 00eh, 063h, 000h, 000h, 000h ; eisa id: csc0000 db 082h, 007h, 000h, wss/sb, 000h ; ansi id db 031h, 000h ; df best choice db 02ah, 002h, 028h ; dma: 1 - wss & sbpro db 02ah, 009h, 028h ; dma: 0,3 - wss & sbpro capture db 022h, 020h, 000h ; irq: 5 interrupt select 0 db 047h, 001h, 034h, 005h, 034h, 005h, 004h, 004h ;16b wssbase: 534 db 047h, 001h, 088h, 003h, 088h, 003h, 008h, 004h ;16b synbase: 388 db 047h, 001h, 020h, 002h, 020h, 002h, 020h, 010h ;16b sbbase: 220 db 031h, 001h ; df acceptable choice 1 db 02ah, 00ah, 028h ; dma: 1,3 - wss & sbpro db 02ah, 00bh, 028h ; dma: 0,1,3 - wss & sbpro capture db 022h, 0a0h, 09ah ; irq: 5,7,9,11,12,15 interrupt select 0 CS4235 crystalclear low cost isa audio system tm ds252pp2 91 db 047h, 001h, 034h, 005h, 0fch, 00fh, 004h, 004h ;16b wssbase: 534-ffc db 047h, 001h, 088h, 003h, 088h, 003h, 008h, 004h ;16b synbase: 388 db 047h, 001h, 020h, 002h, 060h, 002h, 020h, 010h ;16b sbbase: 220-260 db 031h, 002h ; df suboptimal choice 1 db 02ah, 00bh, 028h ; dma: 0,1,3 - wss & sbpro db 022h, 0a0h, 09ah ; irq: 5,7,9,11,12,15 interrupt select 0 db 047h, 001h, 034h, 005h, 0fch, 00fh, 004h, 004h ;16b wssbase: 534-ffc db 047h, 001h, 088h, 003h, 0f8h, 003h, 008h, 004h ;16b synbase: 388-3f8 db 047h, 001h, 020h, 002h, 000h, 003h, 020h, 010h ;16b sbbase: 220-300 db 038h ; end of df for logical device 0 ; logical device 1 (game port) db 015h, 00eh, 063h, 000h, 001h, 000h ; eisa id: csc0001 db 082h, 005h, 000h, game, 000h ; ansi id db 031h, 000h ; df best choice db 047h, 001h, 000h, 002h, 000h, 002h, 008h, 008h ;16b gamebase: 200 db 031h, 001h ; df acceptable choice 1 db 047h, 001h, 008h, 002h, 008h, 002h, 008h, 008h ;16b gamebase: 208 db 038h ; end of df for logical device 1 ; logical device 2 (control) db 015h, 00eh, 063h, 000h, 010h, 000h ; eisa id: csc0010 db 082h, 005h, 000h, ctrl, 000h ; ansi id db 047h, 001h, 020h, 001h, 0f8h, 00fh, 008h, 008h ;16b ctrlbase: 120-ff8 ; logical device 3 (mpu-401) db 015h, 00eh, 063h, 000h, 003h, 000h ; eisa id: csc0003 db 082h, 004h, 000h, mpu, 000h ; ansi id db 031h, 000h ; df best choice db 022h, 000h, 002h ; irq: 9 interrupt select 0 db 047h, 001h, 030h, 003h, 030h, 003h, 008h, 002h ;16b mpubase: 330 db 031h, 001h ; df acceptable choice 1 db 022h, 000h, 09ah ; irq: 9,11,12,15 interrupt select 0 db 047h, 001h, 030h, 003h, 060h, 003h, 008h, 002h ;16b mpubase: 330-360 db 031h, 002h ; df suboptimal choice 1 db 047h, 001h, 030h, 003h, 0e0h, 003h, 008h, 002h ;16b mpubase: 330-3e0 db 038h ; end of df for logical device 3 db 079h, 09ah ; end of resource data, resource size = 280 CS4235 crystalclear low cost isa audio system tm 92 ds252pp2 appendix b: differences between the cs423xb devices and the CS4235 this part is designed to be hardware backwards compatible with some cs423xb designs, primarily motherbaord applications. new drivers will be needed to support this part. hardware pin differences: 1. rfilt and lfilt capacitors are no longer needed and should be removed. on the CS4235, these pins are renamed flti and flto and should have a capacitor placed between them. they are used for the crystal 3d sound circuitry. not populating this capacitor will not have any adverse affects on the part, but will result in non-optimum 3d sound. 2. the external l/rline analog inputs are no longer supported. lline is now flt3d and is used for the 3d sound function. a 0.01 m f capacitor should be placed between this pin and analog ground. when external analog wavetable is desired, the aux1 analog inputs should be used. 3. the analog microphone inputs are now mono. lmic is changed to mic, and rmic has been re- moved. 4 mono out, mout, has been removed. the pin is redefined as apsel and used to change the ad- dress port. apsel has an internal pullup, setting the address port to 0x279 for backwards compatibility. 5. vdf4 has been changed to irqg - a seventh interrupt (typically used for int 10). the default is disabled to provide backwards compatibility. 6. the modem logical device has been removed. this includes mcs and mint. 7. support for an external synthesizer has been removed. this includes scs and sint. 8. the peripheral port has been removed. this includes xd<7:0>, xior, xiow, xa<0:2>. cdrom applications must now drive the isa bus directly or through buffers. 9. the hardware strap enable for the cdrom has been moved. cs423xb designs have a pulldown on xior. to support the cdrom interface on the CS4235, the pulldown must be moved to the mclk pin. also, to enable the alternate cdrom chip select pin acdcs, a pulldown must be added to pin sdout. 10. the dsp serial port is no longer supported as an option on the 2nd joystick connector. the dsp port is still located on pins 4 through 7. 11. there is no 3.3 v isa support. 12. the consumer iec-958 (s/pdif) output, supported on the cs4237b and cs4238b, has been re- moved. 13. only two modes of hardware volume control are supported: 2-button, and 3-button with momen- tary mute. in addition, a 10 nf capacitor to ground is required for switch debounce on the CS4235. 14. pullup resistors have been added to the 4 joystick button pins, 3 hardware volume control pins, and the midin pin. CS4235 crystalclear low cost isa audio system tm ds252pp2 93 |
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